Author | Subject | Date |
A. D. Shripadaraj |
| Re: [SI-LIST] : HSPICE: Delay and invert a differential signal w.r.t to another. | Thu Mar 02 2000 - 01:29:21 PST |
Abd ul-Rahman Lomax |
| Re: [SI-LIST] : different 4-layer board Stack up (S-P-G-S) ? | Tue Mar 07 2000 - 12:58:40 PST |
| [SI-LIST] : 20H rule: a theory? | Wed Feb 02 2000 - 13:27:35 PST |
Abe Riazi |
| RE: [SI-LIST] : Catching the Corners | Sun Mar 19 2000 - 10:43:25 PST |
| RE: [SI-LIST] : Bad IBIS models! | Sat Mar 18 2000 - 12:57:24 PST |
| [SI-LIST] : Catching the Corners | Sat Mar 18 2000 - 12:28:07 PST |
| RE: [SI-LIST] : Searching XTK utils. | Wed Feb 23 2000 - 10:59:49 PST |
| RE: [SI-LIST] : High Speed Design by Rules of Thumb vs. Simulation | Mon Feb 21 2000 - 11:03:07 PST |
| RE: [SI-LIST] : High Speed Design by Rules of Thumb vs. Simulation | Sun Feb 20 2000 - 08:48:00 PST |
| [SI-LIST] : High Speed Design by Rules of Thumb vs. Simulation | Sat Feb 19 2000 - 08:37:19 PST |
| RE: [SI-LIST] : Simulations | Sun Jan 16 2000 - 18:46:04 PST |
| RE: [SI-LIST] : Clamp diodes in models | Sun Jan 09 2000 - 23:54:29 PST |
| RE: [SI-LIST] : Input switching threshold & CPCI | Fri Jan 07 2000 - 17:13:14 PST |
| RE: [SI-LIST] : Input switching threshold & CPCI | Wed Jan 05 2000 - 10:27:01 PST |
| RE: [SI-LIST] : Input switching threshold & CPCI | Tue Jan 04 2000 - 22:57:25 PST |
| RE: [SI-LIST] : Input switching threshold & CPCI | Mon Jan 03 2000 - 09:43:13 PST |
add automation |
| [SI-LIST] : Excessive Posting Length | Sun Jan 16 2000 - 19:59:00 PST |
| Re: [SI-LIST] : Method of measuring characteristics of a capacitor | Fri Jan 07 2000 - 15:57:04 PST |
Adrian Shiner |
| Re: [SI-LIST] : Number of GND/Power pins in a connector ? | Mon Mar 27 2000 - 11:25:54 PST |
| Re: [SI-LIST] : Rambus patent posturing - what gives? | Mon Mar 27 2000 - 11:13:36 PST |
| Re: [SI-LIST] : Analog ground connection on PCBoards | Sun Mar 26 2000 - 11:45:47 PST |
| Re: [SI-LIST] : Number of GND/Power pins in a connector ? | Sat Mar 25 2000 - 04:27:13 PST |
| Re: [SI-LIST] : Number of GND/Power pins in a connector ? | Fri Mar 24 2000 - 11:31:45 PST |
| Re: [SI-LIST] : Bad IBIS models! - Business thoughts | Fri Mar 17 2000 - 11:45:58 PST |
| Re: [SI-LIST] : RE: [IS-LIST] : why .062? | Thu Mar 09 2000 - 12:20:01 PST |
| Re: [SI-LIST] : why .062? | Thu Mar 09 2000 - 12:17:37 PST |
| Re: [SI-LIST] : receiver jitter | Thu Jan 20 2000 - 11:37:11 PST |
| Re: [SI-LIST] : What's your favorite Screwy SI Concept? | Sun Jan 16 2000 - 10:48:23 PST |
| Re: [SI-LIST] : What's your favorite Screwy SI Concept? | Sun Jan 16 2000 - 10:55:02 PST |
| Re: [SI-LIST] : What's your favorite Screwy SI Concept? | Thu Jan 13 2000 - 11:12:59 PST |
| Re: [SI-LIST] : low ESR decoupling capacitors | Fri Jan 07 2000 - 12:52:53 PST |
| Re: [SI-LIST] : What's your favorite Screwy SI Concept? : low ESR decoupling capacitors | Thu Jan 06 2000 - 11:12:48 PST |
| Re: [SI-LIST] : low ESR decoupling capacitors | Thu Jan 06 2000 - 11:10:02 PST |
| Re: [SI-LIST] : Chassis hole opening and frequencies | Wed Jan 05 2000 - 11:33:44 PST |
| Re: [SI-LIST] : What's your favourite Screwy SI Concept? | Wed Jan 05 2000 - 11:57:35 PST |
| Re: [SI-LIST] : Chassis hole opening and frequencies | Wed Jan 05 2000 - 11:40:07 PST |
| Re: [SI-LIST] : Chassis hole opening and frequencies | Wed Jan 05 2000 - 11:50:13 PST |
| Re: [SI-LIST] : Input switching threshold & CPCI | Tue Jan 04 2000 - 13:35:29 PST |
| Re: [SI-LIST] : Input switching threshold & CPCI | Tue Jan 04 2000 - 11:23:24 PST |
| Re: [SI-LIST] : Chassis hole opening and frequencies | Tue Jan 04 2000 - 11:31:30 PST |
| Re: [SI-LIST] : Input switching threshold & CPCI | Mon Jan 03 2000 - 13:06:46 PST |
[email protected] |
| RE: [SI-LIST] : SI Society Chapter | Mon Mar 20 2000 - 12:49:04 PST |
| Re: [SI-LIST] : Fast edges with limited plane capacitance | Fri Mar 17 2000 - 12:17:08 PST |
| Re: [SI-LIST] : SSC | Tue Mar 14 2000 - 08:37:27 PST |
| Re: [SI-LIST] : different 4-layer board Stack up (S-P-G-S) ? | Tue Mar 07 2000 - 10:14:33 PST |
| Re: [SI-LIST] : different 4-layer board Stack up (S-P-G-S) ? | Tue Mar 07 2000 - 09:17:42 PST |
| Re: [SI-LIST] : High-Speed Materials {[DC] & SI-List} | Thu Feb 03 2000 - 11:07:44 PST |
| Re: [SI-LIST] : Possible FAQ Topics | Thu Feb 03 2000 - 11:10:36 PST |
| Re: [SI-LIST] : LVDS signal observation | Wed Feb 02 2000 - 12:52:24 PST |
| Re: [SI-LIST] : What's your favorite Screwy SI Concept? | Thu Jan 13 2000 - 17:31:39 PST |
Alderete, Michael |
| [SI-LIST] : High-Speed Materials {[DC] & SI-List} | Thu Feb 03 2000 - 09:49:24 PST |
| RE: [SI-LIST] : What's your favorite Screwy SI Concept? | Fri Jan 14 2000 - 07:01:10 PST |
| RE: [SI-LIST] : 20H Revisited | Thu Jan 13 2000 - 14:39:50 PST |
Alex Li |
| [SI-LIST] : different 4-layer board Stack up (S-P-G-S) ? | Mon Mar 06 2000 - 18:36:01 PST |
Alex March |
| [SI-LIST] : SPICE models for LVDS and LVPECL | Sun Mar 26 2000 - 03:43:50 PST |
| [SI-LIST] : Lossy line model | Sat Mar 18 2000 - 11:04:59 PST |
Alfredo Moncayo |
| RE: [SI-LIST] : Coplanar Transmission Line | Thu Feb 03 2000 - 12:22:45 PST |
amit agrawal |
| Re: [SI-LIST] : A basic question | Fri Mar 17 2000 - 11:53:25 PST |
| [SI-LIST] : Signal Integrity Positions at Lightsand | Fri Mar 10 2000 - 10:27:52 PST |
Andrew Phillips |
| Re: [SI-LIST] : Parallel Plate Capacitance for Bypass | Wed Apr 12 2000 - 02:27:08 PDT |
| Re: [SI-LIST] : SI FAQ Proposal | Thu Apr 06 2000 - 06:26:06 PDT |
| Re: [SI-LIST] : SI FAQ Proposal | Fri Mar 24 2000 - 06:30:52 PST |
| Re: [SI-LIST] : SI FAQ Proposal | Wed Mar 22 2000 - 06:23:15 PST |
| [SI-LIST] : PCB fabrication technology - what's new? | Fri Mar 03 2000 - 05:30:09 PST |
| [SI-LIST] : What's your favourite Screwy SI Concept? | Wed Jan 05 2000 - 05:17:07 PST |
Andy Peters |
| RE: [SI-LIST] : PLL clock buffer chips and the feedback loop | Thu Apr 06 2000 - 14:58:35 PDT |
| RE: [SI-LIST] : PLL clock buffer chips and the feedback loop | Thu Apr 06 2000 - 13:25:02 PDT |
| [SI-LIST] : re: [SI-LiST]: PLL clock buffer chips and the feedback loop | Wed Apr 05 2000 - 11:48:25 PDT |
| [SI-LIST] : PLL clock buffer chips and the feedback loop | Mon Apr 03 2000 - 11:06:06 PDT |
| [SI-LIST] : RE: | Tue Mar 07 2000 - 13:45:54 PST |
| [SI-LIST] : ACCEL's "signal integrity" tool | Wed Mar 01 2000 - 17:02:44 PST |
apanella |
| Re: [SI-LIST] : via capacitance | Mon Apr 10 2000 - 20:46:40 PDT |
Arani Sinha |
| Re: [SI-LIST] : Field solver | Wed Apr 05 2000 - 13:36:05 PDT |
| Re: [SI-LIST] : Frequency dependence and all that jazz | Wed Jan 26 2000 - 12:02:03 PST |
ARiazi |
| Re: [SI-LIST] : board-level simulation for differential signals | Sat Apr 15 2000 - 07:33:00 PDT |
ARNOLD,PETER (HP-Cupertino,ex3) |
| RE: [SI-LIST] : receiver jitter | Wed Jan 19 2000 - 11:21:27 PST |
| RE: [SI-LIST] : What's your favourite Screwy SI Concept? | Fri Jan 14 2000 - 16:37:45 PST |
Arrigo Benedetti |
| Re: [SI-LIST] : PLL clock buffer chips and the feedback loop | Mon Apr 03 2000 - 11:47:07 PDT |
Aubrey Keith Sparkman |
| Re: [SI-LIST] : Frequency or time domain for componentcharacterization | Mon Feb 28 2000 - 18:37:57 PST |
| Re: [SI-LIST] : What's your favourite Screwy SI Concept? | Mon Jan 10 2000 - 19:34:04 PST |
[email protected] |
| RE: [SI-LIST] : SI Society Chapter | Mon Mar 20 2000 - 11:42:17 PST |
| RE: [SI-LIST] : Frequency or time domain for component characteri zation | Tue Feb 29 2000 - 06:58:30 PST |
| RE: [SI-LIST] : Re: Opportunities | Fri Feb 25 2000 - 16:05:44 PST |
| RE: [SI-LIST] : **error**: internal timestep too small | Thu Jan 20 2000 - 13:04:33 PST |
| RE: [SI-LIST] : What's your favourite Screwy SI Concept? | Mon Jan 17 2000 - 07:33:02 PST |
| RE: [SI-LIST] : What's your favourite Screwy SI Concept? | Fri Jan 14 2000 - 10:20:15 PST |
| RE: [SI-LIST] : low ESR decoupling capacitors | Thu Jan 06 2000 - 11:32:56 PST |
Basker |
| [SI-LIST] : Spice to IBIS Converter | Sat Mar 18 2000 - 11:08:09 PST |
[email protected] |
| Re: [SI-LIST] : 2MM Connectors Standards Committee | Wed Mar 01 2000 - 09:08:25 PST |
| Re: [SI-LIST] : Where for art thou Tantalum Caps? | Fri Feb 18 2000 - 10:34:08 PST |
bgrossma |
| Re: [SI-LIST] : on-chip decoupling capacitance | Wed Apr 12 2000 - 16:43:23 PDT |
| Re: [SI-LIST] : Adding inductors to ground? | Thu Mar 02 2000 - 11:41:17 PST |
| Re: [SI-LIST] : receiver jitter | Wed Jan 19 2000 - 15:14:27 PST |
Bob Davis |
| RE: [SI-LIST] : Number of GND/Power pins in a connector ? | Tue Mar 28 2000 - 00:06:04 PST |
Bob Lewandowski |
| Re: [SI-LIST] : Terminator location with larger BGA's | Fri Apr 07 2000 - 18:52:17 PDT |
| Re: [SI-LIST] : Parallel Plate Capacitance for Bypass | Fri Mar 24 2000 - 15:32:19 PST |
| Re: [SI-LIST] : Lab procedures for TDR | Fri Mar 24 2000 - 09:32:34 PST |
| Re: [SI-LIST] : Hi SI-gurus,One stupid question | Wed Mar 08 2000 - 18:07:04 PST |
| Re: [SI-LIST] : How to measure differential pattern on test coupon? | Thu Mar 02 2000 - 11:36:31 PST |
| Re: [SI-LIST] : Re: Opportunities | Fri Feb 25 2000 - 17:39:13 PST |
| Re: [SI-LIST] : stripline PCB board shrinkage? | Wed Feb 23 2000 - 15:50:12 PST |
| Re: [SI-LIST] : Other ways of transmitting differential signalling besides edgecoupled traces or broad side coupled traces | Thu Feb 17 2000 - 18:56:47 PST |
Bob Perlman |
| [SI-LIST] : Reflections on clock line | Wed Apr 05 2000 - 13:42:44 PDT |
| RE: [SI-LIST] : Bad IBIS models! | Fri Mar 17 2000 - 11:48:12 PST |
| Re: [SI-LIST] : Bad IBIS models! | Wed Mar 15 2000 - 13:33:40 PST |
Bob Ross |
| Re: [SI-LIST] : EUROPEAN IBIS SUMMIT MEETING AGENDA | Tue Apr 04 2000 - 10:53:51 PDT |
| [SI-LIST] : EUROPEAN IBIS SUMMIT MEETING AGENDA | Wed Mar 22 2000 - 11:51:00 PST |
| [SI-LIST] : IBIS EUROPEAN SUMMIT MEETING THIRD ANNOUNCEMENT | Tue Mar 07 2000 - 17:28:19 PST |
| [SI-LIST] : IBIS EUROPEAN SUMMIT MEETING SECOND ANNOUNCEMENT | Wed Feb 16 2000 - 16:16:45 PST |
| [SI-LIST] : EUROPEAN IBIS SUMMIT MEETING ANNOUNCEMENT | Fri Jan 28 2000 - 13:09:02 PST |
Brad Griffin |
| Re: [SI-LIST] : Searching XTK utils. | Wed Feb 23 2000 - 00:43:25 PST |
Bradley S Henson |
| RE: [SI-LIST] : HSPICE Vector File Problem | Mon Apr 17 2000 - 16:15:28 PDT |
| [SI-LIST] : HSPICE Vector File Problem | Mon Apr 17 2000 - 14:09:31 PDT |
| Re: [SI-LIST] : LVDS signal observation | Wed Feb 09 2000 - 07:13:27 PST |
| Re: [SI-LIST] : LVDS signal observation | Wed Feb 02 2000 - 10:51:28 PST |
| Re: [SI-LIST] : Power Plane for Internal Device Power? | Thu Jan 27 2000 - 12:56:22 PST |
| Re: [SI-LIST] : What's your favourite Screwy SI Concept? | Fri Jan 14 2000 - 06:42:54 PST |
| RE: [SI-LIST] : Clamp diodes in models (was Input switching threshold & CPCI) | Mon Jan 10 2000 - 11:06:05 PST |
| Re: [SI-LIST] : Clamp diodes in models (was Input switching threshold & CPCI) | Mon Jan 10 2000 - 08:02:29 PST |
| Re: [SI-LIST] : What's your favorite Screwy SI Concept? | Mon Jan 10 2000 - 07:55:54 PST |
Brent DeWitt |
| RE: [SI-LIST] : PWR/GND grid effect on EMI | Tue Apr 04 2000 - 20:43:21 PDT |
| RE: [SI-LIST] : PWR/GND grid effect on EMI | Tue Apr 04 2000 - 20:24:00 PDT |
| [SI-LIST] : Another capacitor question | Wed Jan 26 2000 - 13:03:42 PST |
[email protected] |
| Re: Fw: [SI-LIST] : via capacitance | Mon Apr 10 2000 - 15:58:22 PDT |
| [SI-LIST] : 0805 quad pack xtalk? | Thu Mar 30 2000 - 14:05:24 PST |
| Re: [SI-LIST] : different 4-layer board Stack up (S-P-G-S) ? | Tue Mar 07 2000 - 09:40:48 PST |
Brian Young |
| Re: [SI-LIST] : Bad IBIS models! | Thu Mar 16 2000 - 07:33:37 PST |
| Re: [SI-LIST] : Bad IBIS models! | Thu Mar 16 2000 - 12:08:39 PST |
| Re: [SI-LIST] : Bad IBIS models! | Thu Mar 16 2000 - 13:08:51 PST |
| Re: [SI-LIST] : A basic question | Fri Mar 17 2000 - 06:19:27 PST |
| Re: [SI-LIST] : A basic question | Fri Mar 17 2000 - 06:30:39 PST |
| Re: [SI-LIST] : Bad IBIS models! | Wed Mar 15 2000 - 15:42:47 PST |
Bruce W. Marler |
| Re: [SI-LIST] : LVDS signal observation | Wed Feb 02 2000 - 12:25:21 PST |
| Re: [SI-LIST] : BERT testers | Wed Jan 19 2000 - 08:44:41 PST |
| Re: [SI-LIST] : High Speed Backplane Connector Recommendations | Mon Jan 17 2000 - 07:45:56 PST |
| Re: [SI-LIST] : High Speed Backplane Connector Recommendations | Sat Jan 15 2000 - 09:47:35 PST |
| Re: [SI-LIST] : High Speed Backplane Connector Recommendations | Fri Jan 14 2000 - 16:06:26 PST |
| Re: [SI-LIST] : High Speed Backplane Connector Recommendations | Thu Jan 13 2000 - 16:43:05 PST |
| Re: [SI-LIST] : High Speed Backplane Connector Recommendations | Thu Jan 13 2000 - 15:37:19 PST |
| [SI-LIST] : High Speed Backplane Connector Recommendations | Thu Jan 13 2000 - 09:40:41 PST |
Bryan Robb |
| [SI-LIST] : AC Coupling vs DC Coupling | Mon Apr 17 2000 - 09:45:25 PDT |
C Deibele |
| Re: [SI-LIST] : Frequency or time domain for component characterization | Tue Feb 29 2000 - 07:20:07 PST |
| Re: [SI-LIST] : Frequency or time domain for component characterization | Mon Feb 28 2000 - 18:36:59 PST |
| Re: [SI-LIST] : stripline PCB board shrinkage? | Thu Feb 24 2000 - 07:06:31 PST |
| Re: [SI-LIST] : stripline PCB board shrinkage? | Wed Feb 23 2000 - 14:15:23 PST |
| [SI-LIST] : stripline PCB board shrinkage? | Wed Feb 23 2000 - 12:48:23 PST |
C. Kumar |
| Re: [SI-LIST] : modeling languages (was: receiver jitter) | Fri Jan 21 2000 - 12:40:33 PST |
| Re: [SI-LIST] : modeling languages (was: receiver jitter) | Fri Jan 21 2000 - 11:44:58 PST |
| Re: [SI-LIST] : modeling languages (was: receiver jitter) | Fri Jan 21 2000 - 10:32:42 PST |
[email protected] |
| Re: [SI-LIST] : anybody fielding newbie questions?? | Mon Apr 17 2000 - 14:45:25 PDT |
| Re: [SI-LIST] : �ظ� [SI-LIST] : Parallel Plate Capacitance for Bypass | Wed Apr 12 2000 - 09:27:33 PDT |
| Re: Fw: [SI-LIST] : via capacitance | Mon Apr 10 2000 - 11:50:55 PDT |
| Re: [SI-LIST] : SI FAQ Proposal | Tue Mar 21 2000 - 17:00:19 PST |
| Re: [SI-LIST] : how to combine multi components together with Orcad layout | Tue Mar 21 2000 - 09:27:25 PST |
| Re: [SI-LIST] : why .062? | Thu Mar 09 2000 - 16:10:20 PST |
| Re: [SI-LIST] : Hatch | Wed Mar 08 2000 - 12:05:15 PST |
| Re: [SI-LIST] :PCB Bd thkness' | Tue Mar 07 2000 - 14:52:34 PST |
| RE: [SI-LIST] : 10 layer board stackup | Fri Jan 21 2000 - 08:48:58 PST |
| Re: [SI-LIST] : What's your favourite Screwy SI Concept and right angle bends? | Fri Jan 14 2000 - 16:09:53 PST |
| RE: [SI-LIST] : What's your favourite Screwy SI Concept? | Fri Jan 14 2000 - 16:08:10 PST |
| RE: [SI-LIST] : What's your favourite Screwy SI Concept? | Thu Jan 13 2000 - 16:45:04 PST |
Chan, Michael |
| RE: [SI-LIST] : 20-H Rule disclosure | Thu Apr 13 2000 - 13:11:32 PDT |
| RE: [SI-LIST] : Power noise/ground bounce software | Fri Feb 04 2000 - 13:45:31 PST |
| RE: [SI-LIST] : **error**: internal timestep too small | Fri Jan 21 2000 - 08:15:02 PST |
| RE: [SI-LIST] : receiver jitter | Wed Jan 19 2000 - 13:31:49 PST |
| RE: [SI-LIST] : receiver jitter | Wed Jan 19 2000 - 11:24:54 PST |
| RE: [SI-LIST] : XTK vs ICX | Fri Jan 14 2000 - 07:29:37 PST |
| RE: [SI-LIST] : What's your favorite Screwy SI Concept? | Tue Jan 11 2000 - 16:17:25 PST |
| RE: [SI-LIST] : What's your favorite Screwy SI Concept? | Fri Jan 07 2000 - 13:21:30 PST |
| RE: [SI-LIST] : Chassis hole opening and frequencies | Tue Jan 04 2000 - 14:25:36 PST |
Chang, Isaac Yew Beng |
| [SI-LIST] : Plane Modeling for big power board plane | Wed Apr 12 2000 - 03:09:09 PDT |
| RE: [SI-LIST] : SI Society Chapter | Mon Mar 20 2000 - 22:03:26 PST |
| [SI-LIST] : Capacitor Characterization Vendor | Thu Feb 10 2000 - 19:58:56 PST |
| [SI-LIST] : Questions abt Power Distribution System | Thu Jan 27 2000 - 23:50:26 PST |
Chang, Martin M |
| RE: [SI-LIST] : Bulk Capacitance | Fri Feb 25 2000 - 11:42:18 PST |
Charles R. Patton |
| [SI-LIST] : Re: [SI-LIST]: Parallel Plate Capacitance for Bypass (air breakdown) | Fri Mar 31 2000 - 15:23:56 PST |
Chris Bobek |
| Re: [SI-LIST] : Adding inductors to ground? | Fri Mar 03 2000 - 08:49:54 PST |
| [SI-LIST] : Adding inductors to ground? | Wed Mar 01 2000 - 14:14:49 PST |
| [SI-LIST] : Zener used to clamp Vcc? | Fri Feb 25 2000 - 14:20:16 PST |
| Re: [SI-LIST] : Decoupling capacitor resonance | Wed Jan 26 2000 - 11:42:36 PST |
| [SI-LIST] : Decoupling capacitor resonance | Tue Jan 25 2000 - 17:42:02 PST |
Chris Cheng |
| RE: [SI-LIST] : on-chip decoupling capacitance (and SI) | Wed Apr 19 2000 - 12:29:04 PDT |
| RE: [SI-LIST] : AC Coupling vs DC Coupling | Tue Apr 18 2000 - 13:25:26 PDT |
| RE: [SI-LIST] : App note assumptions | Fri Apr 14 2000 - 13:29:17 PDT |
| RE: [SI-LIST] : Terminator location with larger BGA's | Fri Apr 07 2000 - 15:45:38 PDT |
| RE: [SI-LIST] : Decoupling strategy on 622MHz devices | Thu Apr 06 2000 - 11:41:18 PDT |
| RE: [SI-LIST] : Field solver | Wed Apr 05 2000 - 15:32:04 PDT |
| RE: [SI-LIST] : [SI-LIST] SI tools | Wed Apr 05 2000 - 15:13:53 PDT |
| RE: [SI-LIST] : Return path for stripline, two ground planes or o ne power and one ground? | Tue Apr 04 2000 - 12:25:54 PDT |
| Re : [SI-LIST] : Bad IBIS models! | Fri Mar 17 2000 - 15:21:23 PST |
| RE: [SI-LIST] : Fast edges with limited plane capacitance | Fri Mar 17 2000 - 15:07:35 PST |
| RE: [SI-LIST] : VTT supply | Mon Mar 13 2000 - 11:07:32 PST |
| RE: [SI-LIST] : SpectraQuest vs XTK | Tue Mar 07 2000 - 17:36:50 PST |
| RE: [SI-LIST] : Training Suggestions Wanted | Thu Feb 10 2000 - 17:10:09 PST |
| RE: [SI-LIST] : Decoupling capacitor resonance | Wed Jan 26 2000 - 11:58:01 PST |
| RE: [SI-LIST] : modeling languages (was: receiver jitter) | Mon Jan 24 2000 - 14:02:33 PST |
| RE: [SI-LIST] : receiver jitter | Wed Jan 19 2000 - 18:04:47 PST |
| RE: [SI-LIST] : receiver jitter | Wed Jan 19 2000 - 13:28:53 PST |
| RE: [SI-LIST] : receiver jitter | Wed Jan 19 2000 - 12:55:29 PST |
| RE: [SI-LIST] : receiver jitter | Wed Jan 19 2000 - 10:12:11 PST |
| [SI-LIST] : receiver jitter | Mon Jan 17 2000 - 16:51:26 PST |
| RE: [SI-LIST] : What's your favourite Screwy SI Concept? More on Bends/Miters | Fri Jan 14 2000 - 19:36:11 PST |
Chris Hansen |
| RE: [SI-LIST] : EUROPEAN IBIS SUMMIT MEETING AGENDA | Fri Mar 24 2000 - 09:36:54 PST |
Chris Heard |
| RE: [SI-LIST] : What's your favourite Screwy SI Concept? | Sun Jan 16 2000 - 17:37:22 PST |
| RE: [SI-LIST] : What's your favourite Screwy SI Concept? | Mon Jan 10 2000 - 14:35:08 PST |
| RE: [SI-LIST] : What's your favourite Screwy SI Concept? | Mon Jan 10 2000 - 11:10:31 PST |
Chris Padilla |
| [SI-LIST] : Re: [SI-LIST] : �ظ�: [SI-LIST] : Parallel Plate Capacitance for Bypass | Fri Mar 31 2000 - 08:11:56 PST |
| Re: [SI-LIST] : Parallel Plate Capacitance for Bypass | Fri Mar 24 2000 - 15:25:39 PST |
| Re: [SI-LIST] : Parallel Plate Capacitance for Bypass | Fri Mar 24 2000 - 14:54:08 PST |
| Re: [SI-LIST] : SI Society Chapter | Mon Mar 20 2000 - 10:10:19 PST |
| [SI-LIST] : Standard's Lore | Tue Mar 07 2000 - 17:25:08 PST |
| RE: [SI-LIST] :PCB Bd thkness' | Tue Mar 07 2000 - 14:27:43 PST |
| [SI-LIST] : Where for art thou Tantalum Caps? | Thu Feb 17 2000 - 15:06:50 PST |
| Re: [SI-LIST] : si-list subscriber demographics | Thu Feb 10 2000 - 16:50:21 PST |
| Re: [SI-LIST] : Coplanar Transmission Line | Thu Feb 03 2000 - 18:26:57 PST |
Chris Rokusek |
| RE: [SI-LIST] : 20-H Rule and Self-Resonant Frequency of Power Planes | Wed Apr 19 2000 - 16:37:58 PDT |
| RE: [SI-LIST] : IBIS question regards [Falling Waveform] / [Rising Waveform]. | Tue Apr 11 2000 - 15:02:07 PDT |
| RE: [SI-LIST] : CAD for SI, EMC. Hyperlynx experiences. | Thu Feb 17 2000 - 14:51:55 PST |
[email protected] |
| [SI-LIST] : on-chip decoupling capacitance | Wed Apr 12 2000 - 13:26:00 PDT |
| RE: [SI-LIST] : Number of GND/Power pins in a connector ? | Thu Mar 23 2000 - 09:11:26 PST |
| RE: [SI-LIST] : Power noise/ground bounce software | Fri Feb 04 2000 - 14:14:48 PST |
| Re: [SI-LIST] : **error**: internal timestep too small | Fri Jan 21 2000 - 06:59:33 PST |
Christian S. Rode |
| [SI-LIST] : Re: Field Extractor + Simulator | Tue Jan 25 2000 - 16:14:42 PST |
| [SI-LIST] : Field Extractor + Simulator | Tue Jan 25 2000 - 15:10:04 PST |
| [SI-LIST] : Beta Field Extractor | Wed Jan 12 2000 - 05:44:07 PST |
Christian Schuster |
| Re: [SI-LIST] : Your experience with equivalent circuit modeling tools ... | Fri Mar 10 2000 - 05:42:11 PST |
| [SI-LIST] : Your experience with equivalent circuit modeling tools ... | Thu Mar 09 2000 - 00:16:38 PST |
Christopher B Wilson |
| [SI-LIST] : LVDS signal observation | Wed Feb 09 2000 - 17:50:38 PST |
Christopher wilson |
| [SI-LIST] : LVDS signal observation | Wed Feb 02 2000 - 10:05:33 PST |
Chung, Sinh |
| [SI-LIST] : a good SI/Layout book | Thu Apr 06 2000 - 12:05:36 PDT |
| RE: [SI-LIST] : PLL clock buffer chips and the feedback loop | Mon Apr 03 2000 - 12:19:37 PDT |
| RE: [SI-LIST] : PLL clock buffer chips and the feedback loop | Mon Apr 03 2000 - 12:05:27 PDT |
Clewell, Craig W |
| RE: [SI-LIST] : Dielectric Material Comparison | Mon Apr 17 2000 - 05:25:26 PDT |
| RE: [SI-LIST] : a good SI/Layout book | Thu Apr 06 2000 - 13:15:31 PDT |
| RE: [SI-LIST] : SI Society Chapter | Mon Mar 20 2000 - 11:15:16 PST |
| RE: [SI-LIST] : Lossy line model | Mon Mar 20 2000 - 05:46:26 PST |
| RE: [SI-LIST] : A basic question | Fri Mar 17 2000 - 05:39:10 PST |
| RE: [SI-LIST] : ribbon cable models | Fri Mar 10 2000 - 05:35:00 PST |
| RE: [SI-LIST] : ACCEL's "signal integrity" tool | Tue Mar 07 2000 - 12:38:07 PST |
| [SI-LIST] : SI POSITION | Tue Feb 22 2000 - 12:17:41 PST |
| RE: [SI-LIST] : High Density Board to Board Connectors? | Mon Feb 14 2000 - 08:15:35 PST |
| RE: [SI-LIST] : High Density Board to Board Connectors? | Mon Feb 14 2000 - 07:20:09 PST |
| RE: [SI-LIST] : bandwidth saving question | Fri Feb 11 2000 - 05:33:19 PST |
| RE: [SI-LIST] : Distance between Power and Ground planes | Mon Jan 24 2000 - 10:00:52 PST |
Cruz, Jose |
| [SI-LIST] : Bulk Capacitance | Fri Feb 25 2000 - 10:45:02 PST |
| RE: [SI-LIST] : Where for art thou Tantalum Caps? | Thu Feb 17 2000 - 17:31:31 PST |
| RE: [SI-LIST] : Method of measuring characteristics of a capacito r | Sat Jan 08 2000 - 05:48:01 PST |
Cusanelli, Tony |
| RE: [SI-LIST] : why .062? | Thu Mar 09 2000 - 03:08:27 PST |
| RE: [SI-LIST] : 10 layer board stackup | Fri Jan 21 2000 - 05:33:11 PST |
D. C. Sessions |
| Re: [SI-LIST] : on-chip decoupling capacitance (and SI) | Wed Apr 19 2000 - 13:00:28 PDT |
| Re: [SI-LIST] : on-chip decoupling capacitance (and SI) | Wed Apr 19 2000 - 11:57:41 PDT |
| Re: [SI-LIST] : on-chip decoupling capacitance (and SI) | Wed Apr 19 2000 - 10:55:51 PDT |
| Re: [SI-LIST] : AC Coupling vs DC Coupling | Tue Apr 18 2000 - 17:41:05 PDT |
| Re: [SI-LIST] : on-chip decoupling capacitance (and SI) | Tue Apr 18 2000 - 16:51:44 PDT |
| Re: [SI-LIST] : AC Coupling vs DC Coupling | Tue Apr 18 2000 - 10:24:57 PDT |
| Re: [SI-LIST] : IBIS for SSTL_2 | Mon Apr 17 2000 - 10:14:58 PDT |
| Re: [SI-LIST] : on-chip decoupling capacitance | Thu Apr 13 2000 - 11:16:44 PDT |
| Re: [SI-LIST] : Terminator location with larger BGA's | Fri Apr 07 2000 - 16:56:13 PDT |
| Re: [SI-LIST] : Decoupling strategy on 622MHz devices | Thu Apr 06 2000 - 17:49:46 PDT |
| Re: [SI-LIST] : SI FAQ Proposal | Thu Mar 23 2000 - 11:01:57 PST |
| Re: [SI-LIST] : SI FAQ Proposal | Wed Mar 22 2000 - 16:36:36 PST |
| Re: [SI-LIST] : meaning and value of C_comp | Wed Mar 22 2000 - 09:57:41 PST |
| Re: [SI-LIST] : meaning and value of C_comp | Tue Mar 21 2000 - 12:53:40 PST |
| Re: [SI-LIST] : Catching the Corners: chain of synchronizingregisters | Mon Mar 20 2000 - 08:16:24 PST |
| Re: [SI-LIST] : Bad IBIS models! | Mon Mar 20 2000 - 07:23:02 PST |
| Re: [SI-LIST] : Bad IBIS models! | Mon Mar 20 2000 - 07:15:11 PST |
| Re: [SI-LIST] : CDM and HDM models of | Mon Mar 20 2000 - 07:00:42 PST |
| Re: [SI-LIST] : Islands of Power | Fri Mar 03 2000 - 08:07:11 PST |
| Re: [SI-LIST] : Adding inductors to ground? | Thu Mar 02 2000 - 13:45:15 PST |
| Re: [SI-LIST] : Adding inductors to ground? | Wed Mar 01 2000 - 17:48:08 PST |
| Re: [SI-LIST] : Fast edge termination choice | Fri Feb 25 2000 - 14:32:21 PST |
| Re: [SI-LIST] : montonic signals at SDRAM-, SSRAM- and FEPROM-adress inputs | Mon Feb 14 2000 - 09:42:21 PST |
| Re: [SI-LIST] : LVDS questions | Tue Feb 01 2000 - 12:39:18 PST |
| Re: [SI-LIST] : Power Plane for Internal Device Power? | Thu Jan 27 2000 - 14:29:06 PST |
| Re: [SI-LIST] : Power Plane for Internal Device Power? | Thu Jan 27 2000 - 12:18:52 PST |
| Re: [SI-LIST] : modeling languages (was: receiver jitter) | Mon Jan 24 2000 - 07:43:39 PST |
| Re: [SI-LIST] : receiver jitter | Wed Jan 19 2000 - 11:57:14 PST |
| Re: [SI-LIST] : receiver jitter | Wed Jan 19 2000 - 11:52:24 PST |
| Re: [SI-LIST] : receiver jitter | Wed Jan 19 2000 - 11:44:11 PST |
| [SI-LIST] : 20H Revisited | Wed Jan 12 2000 - 09:00:29 PST |
| Re: [SI-LIST] : What's your favourite Screwy SI Concept? | Mon Jan 10 2000 - 14:19:36 PST |
| Re: [SI-LIST] : STTL3 bus terminations | Mon Jan 10 2000 - 14:00:01 PST |
| Re: [SI-LIST] : DesignCon 2000 | Mon Jan 10 2000 - 11:35:00 PST |
| Re: [SI-LIST] : Input switching threshold & CPCI | Thu Jan 06 2000 - 12:23:28 PST |
| Re: [SI-LIST] : low ESR decoupling capacitors | Thu Jan 06 2000 - 11:42:28 PST |
| Re: [SI-LIST] : Input switching threshold & CPCI | Thu Jan 06 2000 - 11:09:59 PST |
| Re: [SI-LIST] : low ESR decoupling capacitors | Wed Jan 05 2000 - 13:00:37 PST |
| Re: [SI-LIST] : Input switching threshold & CPCI | Wed Jan 05 2000 - 11:25:41 PST |
| Re: [SI-LIST] : Input switching threshold & CPCI | Wed Jan 05 2000 - 09:13:47 PST |
| Re: [SI-LIST] : Input switching threshold & CPCI | Tue Jan 04 2000 - 15:08:58 PST |
| Re: [SI-LIST] : Chassis hole opening and frequencies | Tue Jan 04 2000 - 14:56:39 PST |
| Re: [SI-LIST] : Chassis hole opening and frequencies | Tue Jan 04 2000 - 13:51:01 PST |
| Re: [SI-LIST] : Input switching threshold & CPCI | Tue Jan 04 2000 - 13:45:46 PST |
| Re: [SI-LIST] : Input switching threshold & CPCI | Tue Jan 04 2000 - 09:44:51 PST |
| Re: [SI-LIST] : Input switching threshold & CPCI | Mon Jan 03 2000 - 08:39:30 PST |
DAmbrosia, John F |
| [SI-LIST] : BLVDS Hot Swap - Connectors | Fri Apr 14 2000 - 13:18:39 PDT |
| RE: [SI-LIST] : ribbon cable models | Fri Mar 10 2000 - 10:52:14 PST |
| [SI-LIST] : Request for AMP Materials Paper | Fri Feb 04 2000 - 14:20:47 PST |
Dan Bostan |
| RE: [SI-LIST] : Bad IBIS models! | Wed Mar 15 2000 - 13:12:59 PST |
| RE: [SI-LIST] : XTK vs ICX | Fri Jan 14 2000 - 10:02:42 PST |
| Re: [SI-LIST] : SI Manager position | Tue Jan 04 2000 - 18:30:47 PST |
Dan Irish |
| Re: [SI-LIST] : Fun With Stackups again | Fri Mar 24 2000 - 09:41:54 PST |
Dan Swanson |
| RE: [SI-LIST] : Field solver | Wed Apr 05 2000 - 04:52:27 PDT |
| RE: [SI-LIST] : via capacitance | Mon Apr 03 2000 - 04:57:18 PDT |
| RE: [SI-LIST] : Return path for stripline, two ground planes or one power and one ground? | Fri Mar 31 2000 - 04:38:43 PST |
| RE: [SI-LIST] : stripline PCB board shrinkage? | Thu Feb 24 2000 - 04:31:06 PST |
| RE: [SI-LIST] : Coplanar Transmission Line | Thu Feb 03 2000 - 11:28:02 PST |
| RE: [SI-LIST] : Another capacitor question | Thu Jan 27 2000 - 11:56:40 PST |
| RE: [SI-LIST] : Another capacitor question | Thu Jan 27 2000 - 04:38:53 PST |
Daniel Wei |
| RE: [SI-LIST] : board-level simulation for differential signals | Fri Apr 14 2000 - 00:08:37 PDT |
| [SI-LIST] : �^��: [SI-LIST] : board-level simulation or differential signal | Thu Apr 13 2000 - 19:24:16 PDT |
| [SI-LIST] : board-level simulation for differential signals | Thu Apr 13 2000 - 04:45:28 PDT |
Daniel, Erik S. |
| RE: [SI-LIST] : A basic question | Fri Mar 17 2000 - 05:55:48 PST |
| RE: [SI-LIST] : A basic question | Fri Mar 17 2000 - 06:07:48 PST |
| RE: [SI-LIST] : Coplanar Transmission Line | Thu Feb 03 2000 - 13:02:08 PST |
Daren McClearnon |
| Re: [SI-LIST] : Chassis hole opening and frequencies | Tue Jan 04 2000 - 19:54:02 PST |
Dave Graves |
| Re: [SI-LIST] : Analog ground connection on PCBoards | Mon Mar 27 2000 - 10:22:26 PST |
Dave Hoover |
| Re: [SI-LIST] : anybody fielding newbie questions?? | Mon Apr 17 2000 - 13:33:27 PDT |
| Re: [SI-LIST] : 18 layer stackup question | Wed Apr 12 2000 - 09:51:37 PDT |
| RE: [SI-LIST] : Hatch | Mon Apr 10 2000 - 16:48:22 PDT |
| [SI-LIST] : RE: [SI-LIST] : RE: [SI-LIST] : �ظ�: [SI-LIST] : Parallel Plate Capacitance for Bypass | Fri Mar 31 2000 - 08:10:02 PST |
| RE: [SI-LIST] :PCB Bd thkness' | Tue Mar 07 2000 - 14:10:22 PST |
| [SI-LIST] : Zo Variance From Plating Thickness Variation | Fri Jan 14 2000 - 10:48:32 PST |
| RE: [SI-LIST] : What's your favorite Screwy SI Concept? | Thu Jan 06 2000 - 12:42:55 PST |
david gil donate |
| [SI-LIST] : Distance between Power and Ground planes | Mon Jan 24 2000 - 01:57:49 PST |
David Haedge |
| [SI-LIST] : Clamp diodes in models (was Input switchingthreshold & CPCI) | Mon Jan 10 2000 - 09:09:57 PST |
David Instone |
| Re: [SI-LIST] : tracking/oversampling PLL architectures | Thu Mar 09 2000 - 01:56:24 PST |
| Re: [SI-LIST] :PCB Bd thkness' | Wed Mar 08 2000 - 08:21:22 PST |
| Re: [SI-LIST] : different 4-layer board Stack up (S-P-G-S) ? | Wed Mar 08 2000 - 01:55:56 PST |
| Re: [SI-LIST] : How to measure differential pattern on test coupo n? | Thu Mar 02 2000 - 02:18:19 PST |
| Re: [SI-LIST] : LVDS signal observation | Mon Feb 21 2000 - 02:30:29 PST |
| Re: [SI-LIST] : Another capacitor question | Thu Jan 27 2000 - 01:51:20 PST |
| Re: [SI-LIST] : Decoupling capacitor resonance | Wed Jan 26 2000 - 02:11:41 PST |
Degerstrom, Michael J. |
| RE: [SI-LIST] : AC Coupling vs DC Coupling | Mon Apr 17 2000 - 19:13:23 PDT |
| RE: [SI-LIST] : SPICE models for LVDS and LVPECL | Wed Mar 29 2000 - 11:50:06 PST |
| RE: [SI-LIST] : LVDS driving PCML | Fri Mar 10 2000 - 17:44:11 PST |
| RE: [SI-LIST] : LVDS questions | Wed Feb 02 2000 - 12:44:52 PST |
| RE: [SI-LIST] : LVDS signal observation | Wed Feb 02 2000 - 11:55:45 PST |
Dennis Tomlinson |
| [SI-LIST] : Position available | Thu Mar 16 2000 - 09:00:31 PST |
| [SI-LIST] : MPC860 IBIS model | Tue Mar 07 2000 - 09:03:45 PST |
| Re: [SI-LIST] : Gigabit eithernet board. | Mon Feb 07 2000 - 12:31:49 PST |
Dennis Yarak |
| Re: [SI-LIST] : Fast edges with limited plane capacitance | Fri Mar 17 2000 - 13:31:22 PST |
Denomme, Paul S. |
| RE: [SI-LIST] : SI Society Chapter | Mon Mar 20 2000 - 12:50:38 PST |
| RE: [SI-LIST] : SI Society Chapter | Mon Mar 20 2000 - 10:46:11 PST |
Devrim Fidanci |
| [SI-LIST] : (urgent) SI tool demand | Tue Feb 29 2000 - 00:12:36 PST |
Dima Smolyansky |
| Re: [SI-LIST] : Your experience with equivalent circuit modeling tools ... | Fri Mar 10 2000 - 14:17:54 PST |
| Re: [SI-LIST] : Your experience with equivalent circuit modeling tools ... | Thu Mar 09 2000 - 13:34:44 PST |
Dmitri Kuznetsov |
| Re: [SI-LIST] : **error**: internal timestep too small | Wed Jan 19 2000 - 15:59:34 PST |
DORIN OPREA |
| [SI-LIST] : Hatch | Wed Mar 08 2000 - 09:53:37 PST |
Doug Brooks |
| RE: [SI-LIST] : [SI-LIST] SI tools | Wed Apr 05 2000 - 15:08:06 PDT |
| RE: [SI-LIST] : Parallel Plate Capacitance for Bypass | Wed Mar 29 2000 - 10:12:29 PST |
| Re: [SI-LIST] : trace width for clock routing- wider/narrower? | Mon Mar 13 2000 - 12:38:46 PST |
| Re: [SI-LIST] : trace width for clock routing- wider/narrower? | Mon Mar 13 2000 - 10:28:52 PST |
| Re: [SI-LIST] : Software scope, VOM, follow-up answer | Tue Mar 07 2000 - 11:44:36 PST |
| [SI-LIST] : Software scope, VOM | Mon Feb 28 2000 - 16:22:11 PST |
| Re: [SI-LIST] : Anyone interested in Howard's book (will trade for Poon's book) | Tue Feb 22 2000 - 14:12:02 PST |
| [SI-LIST] : ESR and Bypass Caps, revisited and revised | Mon Feb 21 2000 - 15:12:59 PST |
| Re: [SI-LIST] : ESR and bypass caps | Mon Feb 07 2000 - 12:02:51 PST |
| Re: [SI-LIST] : ESR and bypass caps | Fri Feb 04 2000 - 18:17:34 PST |
| Re: [SI-LIST] : ESR and bypass caps | Fri Feb 04 2000 - 16:06:17 PST |
| Re: [SI-LIST] : ESR and bypass caps | Fri Feb 04 2000 - 11:52:55 PST |
| [SI-LIST] : ESR and bypass caps | Thu Feb 03 2000 - 15:38:06 PST |
| Re: [SI-LIST] : Another capacitor question | Thu Jan 27 2000 - 11:17:23 PST |
| Re: [SI-LIST] : What's your favourite Screwy SI Concept? | Wed Jan 05 2000 - 09:46:32 PST |
Doug McKean |
| Re: [SI-LIST] : EMC Issue - servo amplifier | Fri Mar 24 2000 - 16:38:30 PST |
| Re: [SI-LIST] : Number of GND/Power pins in a connector ? | Fri Mar 24 2000 - 12:44:32 PST |
| Re: [SI-LIST] : In search of other lists. | Wed Mar 22 2000 - 11:19:14 PST |
| Re: [SI-LIST] : Fast edges with limited plane capacitance | Fri Mar 17 2000 - 16:13:41 PST |
| Re: [SI-LIST] : SI Software for EMC | Fri Mar 17 2000 - 15:41:05 PST |
| Re: [SI-LIST] : Fast edges with limited plane capacitance | Fri Mar 17 2000 - 12:47:57 PST |
| Re: [SI-LIST] : Fast edges with limited plane capacitance | Fri Mar 17 2000 - 11:02:36 PST |
| Re: [SI-LIST] : Crosstalk graphs | Wed Mar 01 2000 - 16:06:34 PST |
| Re: [SI-LIST] : Hopefully not a controversial question ... | Thu Feb 24 2000 - 13:55:29 PST |
| [SI-LIST] : Hopefully not a controversial question ... | Thu Feb 24 2000 - 11:05:18 PST |
| Re: [SI-LIST] : Stack up | Wed Feb 23 2000 - 16:54:15 PST |
| Re: [SI-LIST] : Stack up | Mon Feb 21 2000 - 15:51:40 PST |
| Re: [SI-LIST] : Distance between Power and Ground planes | Mon Jan 24 2000 - 11:22:53 PST |
| Re: [SI-LIST] : 10 layer board stackup | Fri Jan 21 2000 - 13:36:42 PST |
| Re: [SI-LIST] : BERT testers | Wed Jan 19 2000 - 10:47:54 PST |
| Re: [SI-LIST] : What's your favourite Screwy SI Concept? | Fri Jan 14 2000 - 13:07:04 PST |
| Re: [SI-LIST] : What's your favorite Screwy SI Concept? | Thu Jan 13 2000 - 18:50:29 PST |
| Re: [SI-LIST] : What's your favourite Screwy SI Concept? | Thu Jan 13 2000 - 17:14:35 PST |
| Re: [SI-LIST] : What's your favourite Screwy SI Concept? | Thu Jan 13 2000 - 15:33:57 PST |
Doug Piper |
| [SI-LIST] : 2MM Connectors Standards Committee | Wed Mar 01 2000 - 07:14:51 PST |
| RE: [SI-LIST] : Max Zo of Flat Flexible Cable | Mon Feb 28 2000 - 11:51:27 PST |
| [SI-LIST] : High Density Board to Board Connectors? | Mon Feb 14 2000 - 06:54:19 PST |
| [SI-LIST] : Blind Matable DB-9 connector for Fibre-Channel | Mon Jan 10 2000 - 22:18:51 PST |
Doug Smith |
| Re: [SI-LIST] : LVDS signal observation | Tue Feb 08 2000 - 10:25:24 PST |
| [SI-LIST] : Simulations | Fri Jan 14 2000 - 09:30:05 PST |
| Re: [SI-LIST] : What's your favorite Screwy SI Concept? | Tue Jan 11 2000 - 14:46:24 PST |
| [SI-LIST] : Method of measuring characteristics of a capacitor | Fri Jan 07 2000 - 10:56:10 PST |
| Re: [SI-LIST] : What's your favorite Screwy SI Concept? | Thu Jan 06 2000 - 10:27:43 PST |
Douglas C. Smith |
| Re: [SI-LIST] : ESD evenyt counter | Mon Apr 10 2000 - 23:14:30 PDT |
| [SI-LIST] : Unusual System Glitchs | Sun Mar 19 2000 - 20:27:17 PST |
| [SI-LIST] : correction | Mon Feb 07 2000 - 22:38:59 PST |
| Re: [SI-LIST] : ESR and bypass caps | Sun Feb 06 2000 - 18:53:49 PST |
| Re: [SI-LIST] : ESR and bypass caps | Sat Feb 05 2000 - 06:15:57 PST |
| Re: [SI-LIST] : ESR and bypass caps | Fri Feb 04 2000 - 18:53:32 PST |
| Re: [SI-LIST] : ESR and bypass caps | Fri Feb 04 2000 - 18:45:48 PST |
| Re: [SI-LIST] : Simulations | Sun Jan 16 2000 - 23:05:45 PST |
| Re: [SI-LIST] : Method of measuring characteristics of a capacitor | Sat Jan 08 2000 - 12:38:45 PST |
Douglas McKean |
| Re: [SI-LIST] : What's your favorite Screwy SI Concept? | Wed Jan 05 2000 - 13:39:59 PST |
| Re: [SI-LIST] : Chassis hole opening and frequencies | Tue Jan 04 2000 - 10:02:14 PST |
Dr. Edward P. Sayre |
| Re: [SI-LIST] : 20-H Rule and Self-Resonant Frequency of PowerPlanes | Mon Apr 10 2000 - 11:19:21 PDT |
| Re: [SI-LIST] : What's your favourite Screwy SI Concept? | Wed Jan 05 2000 - 14:19:28 PST |
Dunbar, Tony |
| RE: [SI-LIST] : [SI-LIST] SI tools | Wed Apr 05 2000 - 13:57:37 PDT |
| RE: [SI-LIST] : via capacitance | Sun Apr 02 2000 - 09:32:03 PDT |
| RE: [SI-LIST] : Training Suggestions Wanted | Tue Feb 08 2000 - 10:22:56 PST |
| RE: [SI-LIST] : 10 layer board stackup | Thu Jan 20 2000 - 18:06:57 PST |
e |
| [SI-LIST] : 18 layer stackup question | Wed Apr 12 2000 - 02:36:47 PDT |
| Re: [SI-LIST] : �ظ�: [SI-LIST] : Parallel Plate Capacitance for Bypass | Wed Apr 12 2000 - 02:12:36 PDT |
E Montgomery |
| RE: [SI-LIST] : Coplanar Transmission Line | Fri Feb 04 2000 - 09:41:16 PST |
| Re: [SI-LIST] : High-Speed Materials {[DC] & SI-List} | Thu Feb 03 2000 - 11:40:01 PST |
[email protected] |
| Re: [SI-LIST] : Other ways of transmitting differential signalling besides edgecoupled traces or broad side coupled traces | Fri Feb 18 2000 - 06:30:53 PST |
�B�n�d |
| RE: [SI-LIST] : How to measure differential pattern on test coupo n? | Wed Mar 01 2000 - 18:10:16 PST |
| [SI-LIST] : How to measure differential pattern on test coupon? | Tue Feb 29 2000 - 23:33:53 PST |
Ed Grivna |
| [SI-LIST] : Hi Mr. Peters, I'm sorry that you foind our applications notes so confusing. If you can point out some of the specific areas of ambiguity we will attempt to correct them. With respect to your specific question below, i.e., where do you bring the feedback from, this is actually quite simple. You bring it from which ever pin you want to to achieve the multiply or divide ratio you want. The CY7B991 does not have a fixed output for feedback requirements. This can come from any output pin, and can even come from an external divider. The selection of a feedback output path to use is documented in a number of application notes available from http://www.cypress.com/clock/appnotes.html Regards, Ed Grivna Cypress Semiconductor Data Communications Division > From: "Andy Peters" <[email protected]> > To: <[email protected]> > Subject: [SI-LIST] : PLL clock buffer chips and the feedback loop > Date: Mon, 3 Apr 2000 11:06:06 -0700 > MIME-Version: 1.0 > Content-Transfer-Encoding: 7bit > X-Priority: 3 (Normal) > X-MSMail-Priority: Normal > X-MimeOLE: Produced By Microsoft MimeOLE V4.72.2106.4 > Importance: Normal > > When using "zero-skew" PLL clock buffer chips (such as the Cypress > RoboClock), where do you bring the feedback from? Cypress' data sheets and > app notes are notoriously (and typically, I might add) unclear on this - > they simply indicate that it comes from "one of the outputs." > > For instance, my board has an FPGA that talks to four SDRAM devices. It > seems to me that one buffer output could drive the FPGA's clock pin (via > series termination) and four of the other outputs could drive the four SDRAM > clocks (again, through series terminations). Assume that my clock line > lengths are equal, to minimize board skew. Do I take the feedback from one > of the destination pins, and match the line length? Or is it sufficient to > simply connect one of the outputs to the feedback pin right at the chip? > > Are there any other vendors of these sorts of devices? Spread-spectrum > capability is not required. > > thanks, > > -andy > > ps: I sent a short e-mail to the sales-droids at Accel, asking some simple > questions about their signal integrity tool. Since they were apparently too > busy to bother replying, I am no longer considering their product. > > ----------------------------------------- > Andy Peters > Sr Electrical Engineer > National Optical Astronomy Observatories > 950 N Cherry Ave > Tucson, AZ 85719 > 520 318 8191 > [email protected] > > "Money is property; it is not speech." > -- Justice John Paul Stevens > > > **** To unsubscribe from si-list or si-list-digest: send e-mail to [email protected]. In the BODY of message put: UNSUBSCRIBE si-list or UNSUBSCRIBE si-list-digest, for more help, put HERe: [SI-LIST] : PLL clock buffer chips and the feedback loop | Tue Apr 11 2000 - 12:32:37 PDT |
Eli Fernald |
| [SI-LIST] : Opinions on SI CAE tools | Fri Feb 25 2000 - 15:26:39 PST |
Eric Anderson |
| Re: [SI-LIST] : anybody fielding newbie questions?? | Mon Apr 17 2000 - 15:12:42 PDT |
Eric B. Lewis |
| Re: [SI-LIST] : SI Society Chapter | Mon Mar 20 2000 - 11:17:02 PST |
Eric Bogatin |
| [SI-LIST] : width of the return path | Sun Jan 16 2000 - 08:16:54 PST |
Erik Daniel |
| Re: [SI-LIST] : Chassis hole opening and frequencies | Mon Jan 03 2000 - 06:33:55 PST |
[email protected] |
| Re: [SI-LIST] : 20H Revisited | Fri Jan 14 2000 - 21:14:12 PST |
Farrokh Mottahedin |
| RE: [SI-LIST] : AC Coupling vs DC Coupling | Mon Apr 17 2000 - 12:36:29 PDT |
| RE: [SI-LIST] : ESD evenyt counter | Mon Apr 10 2000 - 10:06:21 PDT |
| RE: [SI-LIST] : Production test of 10/100 ethernet conn ?? | Thu Mar 30 2000 - 13:58:04 PST |
| [SI-LIST] : SI Society Chapter | Mon Mar 20 2000 - 08:54:46 PST |
| RE: [SI-LIST] : What is the IEEE 802.3 (Gigabit Ethernet) reflect or adr? | Tue Feb 29 2000 - 15:08:46 PST |
| RE: [SI-LIST] : RE:High-Speed Materials | Fri Feb 04 2000 - 13:04:53 PST |
| RE: [SI-LIST] : Possible FAQ Topics | Thu Feb 03 2000 - 09:20:39 PST |
| RE: [SI-LIST] : IDE bus question | Tue Jan 25 2000 - 11:54:36 PST |
Fasig, Jonathan L. |
| RE: [SI-LIST] : Lab procedures for TDR | Thu Mar 23 2000 - 05:39:05 PST |
| RE: [SI-LIST] : ribbon cable models | Fri Mar 10 2000 - 05:50:24 PST |
Fethi Bellamine |
| Re: [SI-LIST] : Spice to IBIS Converter | Mon Mar 20 2000 - 06:27:05 PST |
Fokken, Gregg J. |
| RE: [SI-LIST] : Number of GND/Power pins in a connector ? | Thu Mar 23 2000 - 08:15:37 PST |
Francis Chiu |
| Re: [SI-LIST] : BLVDS Hot Swap - Connectors | Fri Apr 14 2000 - 16:27:52 PDT |
| RE: [SI-LIST] : BLVDS Hot Swap | Tue Apr 11 2000 - 15:46:47 PDT |
| [SI-LIST] : BLVDS Hot Swap | Tue Apr 11 2000 - 12:37:48 PDT |
Fred Balistreri |
| Re: [SI-LIST] : Spice to IBIS Converter | Mon Mar 20 2000 - 08:39:28 PST |
| Re: [SI-LIST] : A basic question | Fri Mar 17 2000 - 12:30:57 PST |
| Re: [SI-LIST] : Fast edges with limited plane capacitance | Fri Mar 17 2000 - 11:37:21 PST |
| [SI-LIST] : Re: Differential measurements | Thu Mar 02 2000 - 13:05:00 PST |
| Re: [SI-LIST] : modeling languages (was: receiver jitter) | Mon Jan 24 2000 - 14:29:29 PST |
| [SI-LIST] : Email slip up | Fri Jan 21 2000 - 16:39:36 PST |
| Re: [SI-LIST] : modeling languages (was: receiver jitter) | Fri Jan 21 2000 - 16:19:29 PST |
| Re: [SI-LIST] : modeling languages (was: receiver jitter) | Fri Jan 21 2000 - 13:35:26 PST |
| Re: [SI-LIST] : modeling languages (was: receiver jitter) | Fri Jan 21 2000 - 12:30:34 PST |
| Re: [SI-LIST] : **error**: internal timestep too small | Wed Jan 19 2000 - 16:20:14 PST |
| Re: [SI-LIST] : What's your favourite Screwy SI Concept? | Mon Jan 10 2000 - 14:01:05 PST |
Fred Dehkordi |
| RE: [SI-LIST] : different 4-layer board Stack up (S-P-G-S) ? | Tue Mar 07 2000 - 06:43:23 PST |
Fred Dieckmann |
| [SI-LIST] : Low EMI on Two layers | Fri Feb 04 2000 - 07:21:45 PST |
Fred Rosenberger |
| Re: [SI-LIST] : Dielectric Material Comparison | Fri Apr 14 2000 - 15:07:14 PDT |
gacrowell |
| [SI-LIST] : Opinions on Americom HF Digital Design course? | Fri Mar 03 2000 - 14:57:42 PST |
Gaines, William |
| RE: [SI-LIST] : Number of GND/Power pins in a connector ? | Fri Mar 24 2000 - 08:28:44 PST |
| RE: [SI-LIST] : EMC Issue - servo amplifier | Fri Mar 24 2000 - 07:40:02 PST |
| RE: [SI-LIST] : how to combine multi components together with Orc ad layout | Tue Mar 21 2000 - 09:01:50 PST |
| RE: [SI-LIST] : printed resistors | Thu Mar 16 2000 - 09:45:07 PST |
| RE: [SI-LIST] : why .062? | Thu Mar 09 2000 - 08:41:17 PST |
| RE: [SI-LIST] : PCB fabrication technology - what's new? | Tue Mar 07 2000 - 10:33:56 PST |
Gardiner, Scott |
| [SI-LIST] : Job Opening- Intel Oregon | Wed Jan 26 2000 - 17:37:34 PST |
Gary Steinkogler |
| RE: [SI-LIST] : 10 layer board stackup Revisited | Sun Feb 06 2000 - 21:27:19 PST |
[email protected] |
| Re: [SI-LIST] : meaning and value of C_comp | Tue Mar 21 2000 - 14:13:11 PST |
| [SI-LIST] : Toward better model data... | Mon Mar 20 2000 - 06:53:46 PST |
| Re: [SI-LIST] : What's your favourite Screwy SI Concept? | Wed Jan 05 2000 - 15:22:05 PST |
George Borkowicz |
| RE: [SI-LIST] : Frequency or time domain for component characteri zation | Tue Feb 29 2000 - 11:57:47 PST |
| RE: [SI-LIST] : Hopefully not a controversial question ... | Fri Feb 25 2000 - 06:36:04 PST |
Gerald Johnson |
| Re: [SI-LIST] : Parallel Plate Capacitance for Bypass | Mon Mar 27 2000 - 11:01:33 PST |
| Re: [SI-LIST] : trace width for clock routing- wider/narrower? | Mon Mar 13 2000 - 10:53:19 PST |
Giovanni DiBenedetto |
| Re: [SI-LIST] : how to combine multi components together with Orcad layout | Tue Mar 21 2000 - 13:24:53 PST |
Giri Gopalan |
| RE: [SI-LIST] : Adding inductors to ground? | Wed Mar 01 2000 - 15:58:29 PST |
Grasso, Charles (Chaz) |
| RE: [SI-LIST] : SI FAQ Proposal | Tue Apr 04 2000 - 10:05:36 PDT |
| RE: [SI-LIST] : Parallel Plate Capacitance for Bypass | Tue Mar 28 2000 - 15:11:55 PST |
| RE: [SI-LIST] : trace width for clock routing- wider/narrower? | Tue Mar 14 2000 - 10:39:30 PST |
| RE: [SI-LIST] : Re: Opportunities - Keep them coming!! | Mon Feb 28 2000 - 09:51:07 PST |
| RE: [SI-LIST] : Hopefully not a controversial question ... | Mon Feb 28 2000 - 07:56:27 PST |
| [SI-LIST] : Embedded Capacitance Workshop a reminder | Thu Feb 03 2000 - 15:26:02 PST |
| RE: [SI-LIST] : 10 layer board stackup | Fri Jan 21 2000 - 07:53:35 PST |
| RE: [SI-LIST] : What's your favorite Screwy SI Concept? | Tue Jan 11 2000 - 16:02:53 PST |
greg kimball |
| Re: [SI-LIST] : LVDS signal observation | Wed Feb 02 2000 - 21:03:22 PST |
Greim, Michael |
| RE: [SI-LIST] : AC Coupling vs DC Coupling | Mon Apr 17 2000 - 12:14:40 PDT |
| [SI-LIST] : Question on propagation delay........ | Mon Apr 17 2000 - 10:14:56 PDT |
| RE: [SI-LIST] : Parallel Plate Capacitance for Bypass | Mon Mar 27 2000 - 12:13:22 PST |
| RE: [SI-LIST] : Parallel Plate Capacitance for Bypass | Mon Mar 27 2000 - 11:23:28 PST |
| RE: [SI-LIST] : SI Society Chapter | Mon Mar 20 2000 - 11:01:02 PST |
| RE: [SI-LIST] : LVDS driving PCML | Mon Mar 13 2000 - 05:21:27 PST |
| RE: [SI-LIST] : trace width for clock routing- wider/narrower? | Mon Mar 13 2000 - 05:06:42 PST |
| [SI-LIST] : Looking for Ultra3 SCSI LVDlink routing guidelines....... | Tue Mar 07 2000 - 13:30:08 PST |
| RE: [SI-LIST] : different 4-layer board Stack up (S-P-G-S) ? | Tue Mar 07 2000 - 07:09:18 PST |
| RE: [SI-LIST] : different 4-layer board Stack up (S-P-G-S) ? | Tue Mar 07 2000 - 05:28:51 PST |
| [SI-LIST] : FYI: SPICE coupled w element bug in 99.4 | Thu Mar 02 2000 - 04:41:01 PST |
| [SI-LIST] : Creating and displaying eye diagrams with Avanti HSpice..... | Thu Feb 17 2000 - 11:35:41 PST |
| [SI-LIST] : Looking for ibis reflector subscribing info...... | Fri Feb 11 2000 - 04:44:47 PST |
| RE: [SI-LIST] : interplanar capacitance | Thu Feb 03 2000 - 12:56:49 PST |
| [SI-LIST] : Looking for shielded Din 41612 compatible connector | Tue Feb 01 2000 - 07:43:35 PST |
| RE: [SI-LIST] : Decoupling capacitor resonance | Wed Jan 26 2000 - 06:11:32 PST |
| RE: [SI-LIST] : Physcially-small far-end LVDS terminations? | Mon Jan 10 2000 - 11:58:50 PST |
Guido Hunziker |
| [SI-LIST] : Coax connection to a CPW guide | Thu Mar 30 2000 - 14:08:14 PST |
Haller, Robert |
| RE: [SI-LIST] : GOOD IBIS models! | Fri Mar 17 2000 - 13:12:11 PST |
| RE: [SI-LIST] : What's your favourite Screwy SI Concept? | Thu Jan 06 2000 - 11:35:27 PST |
Hank Zauderer |
| [SI-LIST] : Update on SI manager position... | Wed Jan 05 2000 - 12:24:55 PST |
| [SI-LIST] : SI Manager position | Tue Jan 04 2000 - 17:03:03 PST |
Hans Mellberg |
| Re: [SI-LIST] : Coax connection to a CPW guide | Fri Mar 31 2000 - 07:41:44 PST |
| Re: [SI-LIST] : How to create IEEE SI Society Chapters ? | Tue Mar 21 2000 - 11:05:28 PST |
| [SI-LIST] : March 14, EMC Society Meeting Notice, "Shielding and Grounding for GHz Processors and Beyond" | Thu Mar 09 2000 - 10:48:00 PST |
| RE: [SI-LIST] : RE:High-Speed Materials | Tue Feb 08 2000 - 09:25:13 PST |
| [SI-LIST] : RE:High-Speed Materials | Fri Feb 04 2000 - 12:28:35 PST |
| [SI-LIST] : SSN and Power Plane Bounce, 8th February Presentation | Wed Feb 02 2000 - 17:14:10 PST |
| [SI-LIST] : What's your favourite Screwy SI Concept and right angle bends? | Fri Jan 14 2000 - 12:20:11 PST |
| [SI-LIST] : Re:Santa Clara Valley EMC Meeting Notice 11Jan2000 | Tue Jan 11 2000 - 08:21:10 PST |
| [SI-LIST] : Santa Clara Valley EMC Meeting Notice 11Jan2000 | Mon Jan 10 2000 - 09:48:02 PST |
Hansen, Chris |
| [SI-LIST] : Power Distribution Design | Tue Apr 04 2000 - 10:57:20 PDT |
| [SI-LIST] : Parallel Plate Capacitance for Bypass | Fri Mar 24 2000 - 13:25:51 PST |
[email protected] |
| RE: [SI-LIST] : Adding inductors to ground? | Fri Mar 03 2000 - 08:58:55 PST |
| Re: [SI-LIST] : ACCEL's "signal integrity" tool | Thu Mar 02 2000 - 07:20:14 PST |
[email protected] |
| Re: [SI-LIST] : Coplanar Transmission Line | Thu Feb 03 2000 - 20:34:32 PST |
Harris, George |
| RE: [SI-LIST] : Reflections on clock line | Wed Apr 05 2000 - 13:06:33 PDT |
| RE: [SI-LIST] : Return path for stripline, two ground planes or o ne power and one ground? | Fri Mar 31 2000 - 07:08:08 PST |
| RE: [SI-LIST] : interplanar capacitance | Thu Feb 03 2000 - 14:17:53 PST |
| RE: [SI-LIST] : What's your favourite Screwy SI Concept? | Mon Jan 10 2000 - 14:18:35 PST |
Heiko Dudek |
| Re: [SI-LIST] : Signal traces without reference plane | Tue Feb 08 2000 - 07:35:36 PST |
Heinz Blennemann |
| [SI-LIST] : Re: OPENING: Signal Integrity Engineer, Juniper Networks | Tue Jan 04 2000 - 15:26:47 PST |
[email protected] |
| Re: [SI-LIST] : VTT supply | Mon Mar 13 2000 - 02:14:05 PST |
Ilya Zaverukha |
| [SI-LIST] : PWR/GND grid effect on EMI | Tue Apr 04 2000 - 19:00:39 PDT |
Ingraham, Andrew |
| RE: [SI-LIST] : Question on propagation delay........ | Mon Apr 17 2000 - 12:37:50 PDT |
| RE: [SI-LIST] : Bulk Caps -> Inductor? -> Plane | Tue Apr 11 2000 - 15:38:52 PDT |
| RE: [SI-LIST] : PLL clock buffer chips and the feedback loop | Thu Apr 06 2000 - 05:08:54 PDT |
| RE: [SI-LIST] : Return path for stripline, two ground planes or o ne power and one ground? | Sun Apr 02 2000 - 17:06:00 PDT |
| RE: [SI-LIST] : HSPICE Start Up conditions | Wed Mar 22 2000 - 12:42:52 PST |
| RE: [SI-LIST] : A basic question | Fri Mar 17 2000 - 06:56:47 PST |
| RE: [SI-LIST] : Your experience with equivalent circuit modeling tools ... | Fri Mar 10 2000 - 10:32:12 PST |
| RE: [SI-LIST] : Hi SI-gurus, One stupid question: Take a long (sa y 10 ft) long rod of perfect conductor (say copper) and connect one of i ts end to the +ve terminal of a battery through a switch. The other end of the battery is grounded to the earth. Now | Thu Mar 09 2000 - 05:55:05 PST |
| RE: [SI-LIST] : Fast edge termination choice | Fri Feb 25 2000 - 14:19:54 PST |
| RE: [SI-LIST] : Power / Ground simulation | Fri Feb 18 2000 - 07:49:11 PST |
| RE: [SI-LIST] : monotonic signals at SDRAM-, SSRAM- and FEPROM-a dress inputs | Mon Feb 14 2000 - 11:05:07 PST |
| RE: [SI-LIST] : environment effects of radiofrequency radiation | Thu Feb 03 2000 - 09:16:14 PST |
| [SI-LIST] : Clamp diodes in models (was Input switching threshold & CPCI) | Sat Jan 08 2000 - 20:23:33 PST |
| RE: [SI-LIST] : Input switching threshold & CPCI | Thu Jan 06 2000 - 12:56:07 PST |
| RE: [SI-LIST] : Input switching threshold & CPCI | Thu Jan 06 2000 - 08:32:42 PST |
| RE: [SI-LIST] : Input switching threshold & CPCI | Thu Jan 06 2000 - 08:21:08 PST |
| RE: [SI-LIST] : Input switching threshold & CPCI | Wed Jan 05 2000 - 09:52:09 PST |
| RE: [SI-LIST] : Input switching threshold & CPCI | Wed Jan 05 2000 - 06:18:28 PST |
Istvan NOVAK |
| Re: [SI-LIST] : SI FAQ Proposal | Sun Mar 26 2000 - 07:19:11 PST |
| Re: [SI-LIST] : SI FAQ Proposal | Wed Mar 22 2000 - 05:19:51 PST |
| Re: [SI-LIST] : Ferrite bead | Fri Mar 17 2000 - 05:00:26 PST |
| Re: [SI-LIST] : ESR and bypass caps | Sun Feb 06 2000 - 21:16:05 PST |
| [SI-LIST] : DesignCon20000 paper posted | Sun Feb 06 2000 - 20:53:59 PST |
| Re: [SI-LIST] : Questions abt Power Distribution System | Fri Jan 28 2000 - 04:06:29 PST |
Istvan Novak - Board Design Technology |
| Re: [SI-LIST] : Question on propagation delay........ | Mon Apr 17 2000 - 11:09:19 PDT |
| Re: [SI-LIST] : SI Society Chapter | Mon Mar 20 2000 - 09:32:19 PST |
| Re: [SI-LIST] : printed resistors | Thu Mar 16 2000 - 07:32:18 PST |
| RE: [SI-LIST] : Adding inductors to ground? | Thu Mar 02 2000 - 11:56:49 PST |
| Re: [SI-LIST] : ESR and bypass caps | Mon Feb 07 2000 - 11:46:53 PST |
Iulian Ungureanu |
| RE: [SI-LIST] : how to combine multi components together with Orc ad layout | Tue Mar 21 2000 - 09:56:45 PST |
| RE: [SI-LIST] : Stack up | Tue Feb 22 2000 - 09:47:53 PST |
| [SI-LIST] : Stack up | Mon Feb 21 2000 - 11:23:09 PST |
Jagdeep Singh |
| [SI-LIST] : Info about Xilinx Xchecker Cables | Thu Feb 03 2000 - 11:06:45 PST |
James Antonellis - Sun BOS Hardware |
| Re: [SI-LIST] : Board simulations, what should it include? | Tue Mar 14 2000 - 10:24:18 PST |
James F. Peterson |
| RE: [SI-LIST] : XTK vs ICX | Wed Jan 19 2000 - 13:08:52 PST |
Jan Vercammen |
| Re: [SI-LIST] : on-chip decoupling capacitance | Thu Apr 13 2000 - 04:01:18 PDT |
| [SI-LIST] : ESD evenyt counter | Mon Apr 10 2000 - 05:55:46 PDT |
| [SI-LIST] : CDM and HDM models of | Wed Mar 15 2000 - 00:52:34 PST |
Jay Chesavage |
| Re: [SI-LIST] : What's your favorite Screwy SI Concept? | Sun Jan 09 2000 - 01:25:21 PST |
| Re: [SI-LIST] : Chassis hole opening and frequencies | Thu Jan 06 2000 - 05:40:48 PST |
| Re: [SI-LIST] : Chassis hole opening and frequencies | Tue Jan 04 2000 - 13:23:28 PST |
[email protected] |
| Re: [SI-LIST] : BERT testers | Wed Jan 19 2000 - 11:45:04 PST |
Jeff |
| Re: [SI-LIST] : SI Society Chapter | Tue Mar 21 2000 - 20:25:28 PST |
| RE: [SI-LIST] : VTT supply | Tue Mar 14 2000 - 23:09:49 PST |
| Re: [SI-LIST] : VTT supply | Tue Mar 14 2000 - 22:56:14 PST |
| Re: [SI-LIST] : SSC | Tue Mar 14 2000 - 22:49:01 PST |
| RE: [SI-LIST] : tracking/oversampling PLL architectures | Tue Mar 14 2000 - 22:24:30 PST |
| [SI-LIST] : VTT supply | Sun Mar 12 2000 - 23:55:52 PST |
Jeff Reeve |
| Re: [SI-LIST] : Daisy-Chain | Mon Mar 20 2000 - 09:28:09 PST |
Jeff Seeger |
| Re: [SI-LIST] : What's your favourite Screwy SI Concept? | Fri Jan 14 2000 - 10:05:19 PST |
Jeffrey J. Cook |
| [SI-LIST] : [SI-LIST] SI tools | Wed Apr 05 2000 - 13:42:17 PDT |
[email protected] |
| RE: [SI-LIST] :PCB Bd thkness' | Tue Mar 07 2000 - 14:52:49 PST |
Jeremy Plunkett |
| RE: [SI-LIST] : A excellent SI Engineer position in China | Mon Feb 28 2000 - 18:47:00 PST |
| [SI-LIST] : Opportunities at Serverworks (skip the previous) | Mon Feb 28 2000 - 15:44:44 PST |
| RE: [SI-LIST] : 20H rule: a theory? | Wed Jan 12 2000 - 12:24:15 PST |
Jeremy Stover |
| RE: [SI-LIST] : FCAL DB9 cable shield | Mon Jan 10 2000 - 11:27:34 PST |
Jerry Johnson |
| Re: [SI-LIST] : Parallel Plate Capacitance for Bypass | Wed Mar 29 2000 - 17:34:38 PST |
Jian Zheng |
| RE: [SI-LIST] : A basic question | Fri Mar 17 2000 - 08:39:02 PST |
| RE: [SI-LIST] : Coplanar Transmission Line | Fri Feb 04 2000 - 10:11:52 PST |
| RE: [SI-LIST] : Coplanar Transmission Line | Fri Feb 04 2000 - 08:43:05 PST |
| RE: [SI-LIST] : Coplanar Transmission Line | Fri Feb 04 2000 - 08:40:07 PST |
| RE: [SI-LIST] : Coplanar Transmission Line | Fri Feb 04 2000 - 08:29:59 PST |
| RE: [SI-LIST] : Coplanar Transmission Line | Fri Feb 04 2000 - 08:20:46 PST |
| RE: [SI-LIST] : Coplanar Transmission Line | Thu Feb 03 2000 - 17:19:56 PST |
| RE: [SI-LIST] : Coplanar Transmission Line | Thu Feb 03 2000 - 12:38:48 PST |
| RE: [SI-LIST] : What's your favourite Screwy SI Concept? | Fri Jan 14 2000 - 11:10:25 PST |
| RE: [SI-LIST] : What's your favourite Screwy SI Concept? | Fri Jan 14 2000 - 09:58:54 PST |
| RE: [SI-LIST] : What's your favourite Screwy SI Concept? | Thu Jan 13 2000 - 16:32:30 PST |
| RE: [SI-LIST] : Chassis hole opening and frequencies | Mon Jan 10 2000 - 14:29:43 PST |
Jim Freeman |
| Re: [SI-LIST] : Differential LVPECL termination | Thu Mar 30 2000 - 13:16:13 PST |
| Re: [SI-LIST] : Number of GND/Power pins in a connector ? | Thu Mar 23 2000 - 16:50:07 PST |
| Re: [SI-LIST] : Number of GND/Power pins in a connector ? | Thu Mar 23 2000 - 15:29:00 PST |
| Re: [SI-LIST] : Number of GND/Power pins in a connector ? | Thu Mar 23 2000 - 13:15:07 PST |
| Re: [SI-LIST] : Daisy-Chain | Mon Mar 20 2000 - 11:22:21 PST |
| Re: [SI-LIST] : DesignCon20000 paper posted | Mon Feb 07 2000 - 11:04:13 PST |
| Re: [SI-LIST] : modeling languages (was: receiver jitter) | Fri Jan 21 2000 - 17:39:23 PST |
| Re: [SI-LIST] : modeling languages (was: receiver jitter) | Fri Jan 21 2000 - 14:35:33 PST |
| Re: [SI-LIST] : modeling languages (was: receiver jitter) | Fri Jan 21 2000 - 12:20:20 PST |
| Re: [SI-LIST] : modeling languages (was: receiver jitter) | Fri Jan 21 2000 - 09:24:36 PST |
| Re: [SI-LIST] : receiver jitter | Wed Jan 19 2000 - 14:37:48 PST |
| Re: [SI-LIST] : receiver jitter | Wed Jan 19 2000 - 12:00:35 PST |
| Re: [SI-LIST] : What's your favorite Screwy SI Concept? | Fri Jan 14 2000 - 14:15:05 PST |
Jim Leng |
| Re: [SI-LIST] : Number of GND/Power pins in a connector ? | Mon Mar 27 2000 - 10:41:31 PST |
[email protected] |
| RE: [SI-LIST] : LVDS signal observation | Wed Feb 02 2000 - 13:39:33 PST |
[email protected] |
| RE: [SI-LIST] : ESR and bypass caps | Wed Feb 16 2000 - 13:57:42 PST |
JOACHIM MUELLER |
| [SI-LIST] : OPENING SI Engineer | Tue Jan 04 2000 - 06:39:56 PST |
Joe Socha |
| RE: [SI-LIST] : Searching XTK utils. | Wed Feb 23 2000 - 12:01:43 PST |
Joel Jorgenson |
| Re: [SI-LIST] : Re: [SI-LIST] : �ظ�: [SI-LIST] : Parallel Plate Capacitance for Bypass | Fri Mar 31 2000 - 08:32:34 PST |
Joel Kolstad |
| RE: [SI-LIST] : Physcially-small far-end LVDS terminations? | Mon Jan 10 2000 - 10:51:39 PST |
John Draut |
| RE: [SI-LIST] : re: [SI-LiST]: PLL clock buffer chips and the fee dback loop | Wed Apr 05 2000 - 12:15:12 PDT |
John Ellis |
| RE: [SI-LIST] : Max Zo of Flat Flexible Cable | Mon Feb 28 2000 - 08:10:34 PST |
| RE: [SI-LIST] : High Speed Backplane Connector Recommendations | Fri Jan 14 2000 - 04:38:53 PST |
John Howard |
| Re: [SI-LIST] : 20-H Rule and Self-Resonant Frequency of Power Planes | Thu Mar 30 2000 - 06:39:57 PST |
| Re: [SI-LIST] : Training Suggestions Wanted | Thu Feb 10 2000 - 11:05:40 PST |
| Re: [SI-LIST] : EMC techniques on 2-layer board | Fri Feb 04 2000 - 00:10:05 PST |
| Re: [SI-LIST] : Coplanar Transmission Line | Thu Feb 03 2000 - 08:52:42 PST |
| Re: [SI-LIST] : What's your favorite Screwy SI Concept? | Thu Jan 13 2000 - 11:25:05 PST |
John Phillips |
| RE: [SI-LIST] : Bad IBIS models! | Thu Mar 16 2000 - 01:32:38 PST |
| RE: [SI-LIST] : ESR and bypass caps | Mon Feb 07 2000 - 06:53:30 PST |
| RE: [SI-LIST] : High-Speed Materials {[DC] & SI-List} | Fri Feb 04 2000 - 01:51:19 PST |
John, Hans-Joerg |
| AW: [SI-LIST] : How to measure differential pattern on test coupo n? | Wed Mar 01 2000 - 01:15:06 PST |
[email protected] |
| [SI-LIST] : Low Inductance | Thu Apr 06 2000 - 10:38:10 PDT |
Johns Daniel |
| RE: [SI-LIST] : 10 layer board stackup | Fri Jan 21 2000 - 10:48:24 PST |
Jon Keeble |
| Fw: [SI-LIST] : via capacitance | Fri Mar 31 2000 - 18:40:23 PST |
| Re: [SI-LIST] : how to combine multi components together with Orcad layout | Wed Mar 22 2000 - 20:22:49 PST |
| Re: [SI-LIST] : High Speed Backplane Connector Recommendations | Fri Jan 14 2000 - 03:23:30 PST |
| Re: [SI-LIST] : High Speed Backplane Connector Recommendations | Thu Jan 13 2000 - 13:25:00 PST |
Jon Powell |
| RE: [SI-LIST] : Software scope, VOM | Tue Mar 07 2000 - 10:57:06 PST |
| [SI-LIST] : positions available | Mon Jan 10 2000 - 11:14:54 PST |
| Re: [SI-LIST] : What's your favorite Screwy SI Concept? | Thu Jan 06 2000 - 10:49:53 PST |
| Re: [SI-LIST] : What's your favorite Screwy SI Concept? | Wed Jan 05 2000 - 16:12:49 PST |
Jonathan Dowling |
| Re: [SI-LIST] : board-level simulation for differential signals | Mon Apr 17 2000 - 17:11:19 PDT |
| [SI-LIST] : Signal Integrity Positions at AMD -- Austin, TX | Mon Mar 20 2000 - 09:09:19 PST |
| RE: [SI-LIST] :What do inputs do? monotonic signals at SDRAM-, SSRAM - and FEPROM-a dress inputs | Thu Feb 24 2000 - 09:09:27 PST |
| RE: [SI-LIST] : receiver jitter | Wed Jan 19 2000 - 10:26:47 PST |
| Re: [SI-LIST] : receiver jitter | Tue Jan 18 2000 - 17:57:18 PST |
Jones, Matthew S |
| RE: [SI-LIST] : Signal Integrity Position | Fri Mar 31 2000 - 08:15:22 PST |
Jose Rodriguez |
| [SI-LIST] : CAD for SI, EMC. Hyperlynx experiences. | Thu Feb 17 2000 - 12:17:18 PST |
| Re: [SI-LIST] : Capacitor Characterization Vendor | Fri Feb 11 2000 - 09:50:54 PST |
Josip Popovic |
| Re: [SI-LIST] : AC Coupling vs DC Coupling | Tue Apr 18 2000 - 04:57:50 PDT |
[email protected] |
| Re: [SI-LIST] : Dielectric Material Comparison | Tue Apr 18 2000 - 07:38:30 PDT |
| RE: [SI-LIST] : Return path for stripline, two ground planes or o ne power and one ground? | Wed Apr 12 2000 - 05:33:16 PDT |
| [SI-LIST] : Information on FR-4 and other PCB dielectric materials | Wed Apr 12 2000 - 06:24:34 PDT |
| Re: [SI-LIST] : Bulk Caps -> Inductor? -> Plane | Tue Apr 11 2000 - 13:53:23 PDT |
| Re: [SI-LIST] : a good SI/Layout book | Thu Apr 06 2000 - 13:27:46 PDT |
| Re: [SI-LIST] : PWR/GND grid effect on EMI | Wed Apr 05 2000 - 08:39:45 PDT |
| [SI-LIST] : 20-H Rule and Self-Resonant Frequency of Power Planes | Thu Mar 30 2000 - 05:06:00 PST |
| Re: [SI-LIST] : Parallel Plate Capacitance for Bypass | Mon Mar 27 2000 - 05:57:04 PST |
| RE: [SI-LIST] : Fast edges with limited plane capacitance | Mon Mar 20 2000 - 08:49:40 PST |
| Re: [SI-LIST] : 2 Layer Boards and Ground Grids | Tue Mar 14 2000 - 09:28:21 PST |
| RE: [SI-LIST] : Clamp diodes in models (was Input switching threshold & CPCI) | Mon Jan 10 2000 - 13:22:20 PST |
| Re: [SI-LIST] : Clamp diodes in models (was Input switchingthreshold & CPCI) | Mon Jan 10 2000 - 11:50:36 PST |
Julia Nekrylova |
| [SI-LIST] : LVDS driving PCML | Wed Mar 08 2000 - 18:41:26 PST |
jwalden |
| RE: [SI-LIST] : different 4-layer board Stack up (S-P-G-S) ? | Tue Mar 07 2000 - 11:51:49 PST |
Kai Keskinen |
| RE: [SI-LIST] : Number of GND/Power pins in a connector ? | Fri Mar 24 2000 - 11:51:38 PST |
| RE: [SI-LIST] : Number of GND/Power pins in a connector ? | Fri Mar 24 2000 - 10:49:08 PST |
| RE: [SI-LIST] : HSPICE Start Up conditions | Thu Mar 23 2000 - 04:20:03 PST |
| RE: [SI-LIST] : HSPICE Start Up conditions | Wed Mar 22 2000 - 11:15:27 PST |
| [SI-LIST] : HSPICE Start Up conditions | Wed Mar 22 2000 - 07:45:53 PST |
| RE: [SI-LIST] : ribbon cable models | Fri Mar 10 2000 - 10:33:37 PST |
| RE: [SI-LIST] : PCB fabrication technology - what's new? | Fri Mar 03 2000 - 08:00:52 PST |
| [SI-LIST] : Frequency or time domain for component characterization | Mon Feb 28 2000 - 12:09:12 PST |
Keith Amundsen |
| RE: [SI-LIST] : tracking/oversampling PLL architectures | Tue Mar 14 2000 - 07:35:21 PST |
| RE: [SI-LIST] : tracking/oversampling PLL architectures | Mon Mar 13 2000 - 12:01:08 PST |
| [SI-LIST] : RE: +AFs-SI-LIST+AF0- : Where can I get some design informations about CPCI? | Thu Mar 09 2000 - 13:57:31 PST |
| [SI-LIST] : Islands of Power | Fri Mar 03 2000 - 06:49:01 PST |
Ken Wu |
| [SI-LIST] : factors affecting source synchronus timing | Tue Mar 07 2000 - 13:49:27 PST |
Kevin Daily |
| [SI-LIST] : PADS PowerPCB + SPECCTRA FST Circuit Fire Sale | Tue Feb 15 2000 - 12:02:03 PST |
Kevin Dale Kirmse |
| [SI-LIST] : Lab procedures for TDR | Wed Mar 22 2000 - 21:13:23 PST |
Kevin Hansen |
| [SI-LIST] : SI Speaker Feedback | Wed Feb 02 2000 - 12:54:03 PST |
[email protected] |
| RE: [SI-LIST] : A basic question | Fri Mar 17 2000 - 08:06:20 PST |
| Re: [SI-LIST] : A basic question | Fri Mar 17 2000 - 05:31:40 PST |
Killoy Richard-P29744 |
| RE: [SI-LIST] :PCB Bd thkness' | Wed Mar 08 2000 - 07:32:19 PST |
Kim Helliwell |
| [SI-LIST] : Field solver | Tue Apr 04 2000 - 15:04:58 PDT |
| Re: [SI-LIST] : Signal Integrity Position | Fri Mar 31 2000 - 07:54:30 PST |
| Re: [SI-LIST] : SI Society Chapter | Mon Mar 20 2000 - 14:15:58 PST |
| Re: [SI-LIST] : Bad IBIS models! | Fri Mar 17 2000 - 11:33:00 PST |
| Re: [SI-LIST] : Bad IBIS models! | Thu Mar 16 2000 - 09:50:02 PST |
| Re: [SI-LIST] : Bad IBIS models! | Thu Mar 16 2000 - 14:15:58 PST |
| Re: [SI-LIST] : Bad IBIS models! | Wed Mar 15 2000 - 15:10:44 PST |
| [SI-LIST] : Bad IBIS models! | Wed Mar 15 2000 - 12:53:59 PST |
| Re: [SI-LIST] : Bad IBIS models! | Wed Mar 15 2000 - 14:03:03 PST |
| Re: [SI-LIST] : Bad IBIS models! | Wed Mar 15 2000 - 14:08:25 PST |
| Re: [SI-LIST] : Bad IBIS models! | Wed Mar 15 2000 - 14:29:28 PST |
| Re: [SI-LIST] : Bad IBIS models! | Wed Mar 15 2000 - 14:24:37 PST |
| Re: [SI-LIST] :PCB Bd thkness' | Wed Mar 08 2000 - 08:48:41 PST |
| Re: [SI-LIST] : modeling languages (was: receiver jitter) | Fri Jan 21 2000 - 13:07:05 PST |
| Re: [SI-LIST] : modeling languages (was: receiver jitter) | Fri Jan 21 2000 - 11:03:49 PST |
| Re: [SI-LIST] : **error**: internal timestep too small | Fri Jan 21 2000 - 08:38:42 PST |
| Re: [SI-LIST] : **error**: internal timestep too small | Thu Jan 20 2000 - 13:41:00 PST |
| Re: [SI-LIST] : **error**: internal timestep too small | Thu Jan 20 2000 - 13:03:26 PST |
| Re: [SI-LIST] : **error**: internal timestep too small | Thu Jan 20 2000 - 10:15:51 PST |
| Re: [SI-LIST] : **error**: internal timestep too small | Wed Jan 19 2000 - 17:13:06 PST |
| Re: [SI-LIST] : **error**: internal timestep too small | Wed Jan 19 2000 - 17:05:45 PST |
| Re: [SI-LIST] : What's your favourite Screwy SI Concept? | Mon Jan 10 2000 - 13:16:42 PST |
Knighten, Jim L |
| RE: [SI-LIST] : 20-H Rule and Self-Resonant Frequency of Power Pl anes | Thu Mar 30 2000 - 13:59:16 PST |
| RE: [SI-LIST] : Parallel Plate Capacitance for Bypass | Fri Mar 24 2000 - 14:44:40 PST |
| RE: [SI-LIST] : SI Software for EMC | Thu Mar 16 2000 - 10:50:29 PST |
[email protected] |
| [SI-LIST] : 10 layer board stackup | Thu Jan 20 2000 - 14:22:31 PST |
Kowal, Keith |
| RE: [SI-LIST] : Fast edge termination choice | Fri Feb 25 2000 - 13:04:53 PST |
Krishnan S Rengarajan |
| Re: [SI-LIST] : CDM and HDM models of | Wed Mar 15 2000 - 03:19:18 PST |
| Re: [SI-LIST] : SSC | Tue Mar 14 2000 - 19:56:52 PST |
| Re: [SI-LIST] : SSC | Mon Mar 13 2000 - 23:55:59 PST |
LaFlamme, Peter |
| RE: [SI-LIST] : Bad IBIS models! GREAT POINTS DC | Mon Mar 20 2000 - 07:37:54 PST |
Larry Miller |
| Re: [SI-LIST] : Low Inductance | Thu Apr 06 2000 - 11:46:13 PDT |
Larry Smith |
| RE: [SI-LIST] : Return path for stripline, two ground planes or o ne power and one ground? | Tue Apr 11 2000 - 14:12:29 PDT |
| Re: [SI-LIST] : Return path for stripline, two ground planes or o ne power and one ground? | Fri Apr 07 2000 - 15:54:10 PDT |
| Re: [SI-LIST] : Return path for stripline, two ground planes or o ne power and one ground? | Tue Apr 04 2000 - 15:09:03 PDT |
| RE: [SI-LIST] : Return path for stripline, two ground planes or o ne power and one ground? | Mon Apr 03 2000 - 10:00:04 PDT |
| Re: [SI-LIST] : Parallel Plate Capacitance for Bypass | Mon Mar 27 2000 - 17:05:14 PST |
| Re: [SI-LIST] : Fast edges with limited plane capacitance | Fri Mar 17 2000 - 13:23:13 PST |
| Re: [SI-LIST] : Fast edges with limited plane capacitance | Fri Mar 17 2000 - 13:18:37 PST |
| Re: [SI-LIST] : Fast edges with limited plane capacitance | Fri Mar 17 2000 - 13:05:02 PST |
| Re: [SI-LIST] : Fast edges with limited plane capacitance | Fri Mar 17 2000 - 12:56:31 PST |
| Re: [SI-LIST] : Fast edges with limited plane capacitance | Fri Mar 17 2000 - 10:17:04 PST |
| RE: [SI-LIST] : A basic question | Fri Mar 17 2000 - 09:42:02 PST |
| Re: [SI-LIST] : Medium range capacitors | Wed Mar 08 2000 - 08:59:46 PST |
| RE: [SI-LIST] : Adding inductors to ground? | Fri Mar 03 2000 - 09:55:16 PST |
| Re: [SI-LIST] : ESR and bypass caps | Mon Feb 07 2000 - 10:21:52 PST |
| Re: [SI-LIST] : ESR and bypass caps | Mon Feb 07 2000 - 09:39:10 PST |
| Re: [SI-LIST] : ESR and bypass caps | Fri Feb 04 2000 - 15:37:18 PST |
| Re: [SI-LIST] : ESR and bypass caps | Fri Feb 04 2000 - 11:06:37 PST |
| RE: [SI-LIST] : Clamp diodes in models (was Input switching threshold & CPCI) | Mon Jan 10 2000 - 12:07:43 PST |
| Re: [SI-LIST] : low ESR decoupling capacitors | Wed Jan 05 2000 - 13:46:08 PST |
| [SI-LIST] : low ESR decoupling capacitors | Wed Jan 05 2000 - 12:19:33 PST |
| Re: [SI-LIST] : What's your favourite Screwy SI Concept? | Wed Jan 05 2000 - 09:25:53 PST |
LATOURRETTE,JEFF (HP-SanJose,ex1) |
| RE: [SI-LIST] : What's your favourite Screwy SI Concept? More on Bends/Miters | Fri Jan 14 2000 - 18:11:29 PST |
| RE: [SI-LIST] : Chassis hole opening and frequencies | Mon Jan 10 2000 - 13:08:11 PST |
| RE: [SI-LIST] : Chassis hole opening and frequencies | Mon Jan 10 2000 - 12:14:23 PST |
| [SI-LIST] : Job Posting: Agilent Technologies (formerly HP) Fiber-Optics App lications Engineers | Thu Jan 06 2000 - 19:15:33 PST |
Laurence Michaels |
| [SI-LIST] : Re: Signal Integrity Position | Fri Mar 31 2000 - 11:14:45 PST |
| Re: [SI-LIST] : Bad IBIS models! | Thu Mar 16 2000 - 06:47:33 PST |
| Re: [SI-LIST] : Re:Training Suggestions Wanted | Wed Feb 09 2000 - 06:00:38 PST |
| Re: [SI-LIST] : Training Suggestions Wanted | Tue Feb 08 2000 - 10:03:51 PST |
| [SI-LIST] : How to find the archives (was Re: Signal Integrity simulation tools) | Wed Feb 02 2000 - 08:02:48 PST |
| Re: [SI-LIST] : XTK vs ICX | Fri Jan 14 2000 - 06:58:06 PST |
Lawrence Butcher |
| Re: [SI-LIST] : PWR/GND grid effect on EMI in 2-layer board | Tue Apr 04 2000 - 20:04:13 PDT |
| [SI-LIST] : Fun With Stackups again | Fri Mar 17 2000 - 12:59:06 PST |
Lawrence Mirabal |
| Re: [SI-LIST] : [SI-LIST] SI tools | Wed Apr 05 2000 - 14:17:01 PDT |
Le, Dat (dle) |
| RE: [SI-LIST] : SpectraQuest vs XTK | Mon Mar 06 2000 - 10:57:39 PST |
Lee Ritchey |
| Re: [SI-LIST] : Stack up | Thu Feb 24 2000 - 08:22:27 PST |
| Re: [SI-LIST] : Stack up | Wed Feb 23 2000 - 07:51:22 PST |
| Re: [SI-LIST] : Stack up | Tue Feb 22 2000 - 07:46:59 PST |
| Re: [SI-LIST] : Training Suggestions Wanted | Fri Feb 11 2000 - 08:10:37 PST |
| Re: [SI-LIST] : 10 layer board stackup Revisited | Wed Feb 09 2000 - 08:14:36 PST |
| Re: [SI-LIST] : SSN and Power Plane Bounce, 8th February Presentation | Thu Feb 03 2000 - 09:02:46 PST |
| Re: [SI-LIST] : Power Plane for Internal Device Power? | Thu Jan 27 2000 - 14:16:10 PST |
| Re: [SI-LIST] : Distance between Power and Ground planes | Mon Jan 24 2000 - 07:57:46 PST |
| Re: [SI-LIST] : 10 layer board stackup | Thu Jan 20 2000 - 17:48:48 PST |
| Re: [SI-LIST] : What's your favourite Screwy SI Concept? | Sat Jan 15 2000 - 12:18:11 PST |
| Re: [SI-LIST] : What's your favourite Screwy SI Concept? | Sat Jan 15 2000 - 12:15:54 PST |
| Re: [SI-LIST] : What's your favourite Screwy SI Concept? | Sat Jan 15 2000 - 12:13:46 PST |
| Re: [SI-LIST] : High Speed Backplane Connector Recommendations | Fri Jan 14 2000 - 08:54:00 PST |
| Re: [SI-LIST] : What's your favourite Screwy SI Concept? | Fri Jan 14 2000 - 08:55:41 PST |
| Re: [SI-LIST] : What's your favourite Screwy SI Concept? | Fri Jan 14 2000 - 08:53:12 PST |
| Re: [SI-LIST] : What's your favourite Screwy SI Concept? | Tue Jan 11 2000 - 08:30:32 PST |
| Re: [SI-LIST] : Physcially-small far-end LVDS terminations? | Tue Jan 11 2000 - 08:19:12 PST |
| Re: [SI-LIST] : What's your favorite Screwy SI Concept? | Tue Jan 11 2000 - 08:09:10 PST |
| Re: [SI-LIST] : Signal traces without reference plane | Tue Jan 11 2000 - 07:54:12 PST |
| Re: [SI-LIST] : 20-H RULE CONTINUED | Mon Jan 10 2000 - 09:05:05 PST |
| Re: [SI-LIST] : What's your favorite Screwy SI Concept? | Mon Jan 10 2000 - 08:52:17 PST |
| Re: [SI-LIST] : What's your favorite Screwy SI Concept? | Mon Jan 10 2000 - 08:53:57 PST |
| Re: [SI-LIST] : What's your favorite Screwy SI Concept? | Sat Jan 08 2000 - 16:53:06 PST |
| Re: [SI-LIST] : What's your favorite Screwy SI Concept? | Thu Jan 06 2000 - 14:57:10 PST |
| Re: [SI-LIST] : What's your favourite Screwy SI Concept? | Wed Jan 05 2000 - 09:25:08 PST |
[email protected] |
| Re: [SI-LIST] : Coax connection to a CPW guide | Fri Mar 31 2000 - 16:22:07 PST |
| Re: [SI-LIST] : Fast edges with limited plane capacitance | Tue Mar 21 2000 - 13:53:16 PST |
| Re: [SI-LIST] : SI Software for EMC | Thu Mar 16 2000 - 09:51:18 PST |
| Re: [SI-LIST] : SSC | Tue Mar 14 2000 - 00:09:51 PST |
| Re: [SI-LIST] : Re: Opportunities | Fri Feb 25 2000 - 18:10:18 PST |
| Re: [SI-LIST] : Training Suggestions Wanted | Thu Feb 10 2000 - 21:52:01 PST |
| Re: [SI-LIST] : SI Manager position | Tue Jan 04 2000 - 18:41:01 PST |
Liang, Hongbo (Subsidiary) |
| RE: [SI-LIST] : SI FAQ Proposal | Thu Mar 23 2000 - 06:26:05 PST |
Lisa Desandoli |
| [SI-LIST] : Dielectric Material Comparison | Fri Apr 14 2000 - 14:40:37 PDT |
| RE: [SI-LIST] : a good SI/Layout book | Thu Apr 06 2000 - 12:26:52 PDT |
Long Wang |
| [SI-LIST] : backward Xtalk? | Mon Jan 10 2000 - 11:30:04 PST |
Loren Koehler |
| [SI-LIST] : What is the IEEE 802.3 (Gigabit Ethernet) reflector adr? | Tue Feb 29 2000 - 11:00:52 PST |
Lukas Louw |
| Re: [SI-LIST] : ACCEL's "signal integrity" tool | Tue Mar 07 2000 - 10:52:07 PST |
Lum Wee Mei |
| [SI-LIST] : EMC Issue - servo amplifier | Thu Mar 23 2000 - 19:08:27 PST |
| Re: [SI-LIST] : Number of GND/Power pins in a connector ? | Thu Mar 23 2000 - 15:18:50 PST |
| Re: [SI-LIST] : SI Society Chapter | Mon Mar 20 2000 - 15:25:40 PST |
| Re: [SI-LIST] :PCB Bd thkness' | Tue Mar 07 2000 - 19:20:35 PST |
| Re: [SI-LIST] : Adding inductors to ground? | Fri Mar 03 2000 - 01:14:48 PST |
Lund, Steve |
| RE: [SI-LIST] : Anyone on SI-list receiving UCE type spam? | Fri Feb 11 2000 - 05:53:00 PST |
Lyke James Civ AFRL/VSSE |
| RE: [SI-LIST] : tracking/oversampling PLL architectures | Mon Mar 13 2000 - 12:26:41 PST |
Lynne Green |
| [SI-LIST] : RE: App Notes & Papers | Mon Apr 17 2000 - 11:30:06 PDT |
| [SI-LIST] : App Notes & Papers | Mon Apr 17 2000 - 11:23:39 PDT |
| RE: [SI-LIST] : PLL clock buffer chips and the feedback loop | Thu Apr 06 2000 - 13:50:59 PDT |
Mackillop, William J. |
| [SI-LIST] : Re:Training Suggestions Wanted | Tue Feb 08 2000 - 11:46:57 PST |
maher musa |
| Re: [SI-LIST] : Signal Integrity Position | Fri Mar 31 2000 - 05:54:10 PST |
| [SI-LIST] : Signal Integrity Position | Thu Mar 30 2000 - 20:33:45 PST |
Mango, Steve |
| [SI-LIST] : SI Design Engineer Position at Stratus (pre-IPO) in Maynard, MA | Sun Feb 20 2000 - 06:08:38 PST |
[email protected] |
| Re: [SI-LIST] : Where for art thou Tantalum Caps? | Thu Feb 17 2000 - 20:20:31 PST |
| [SI-LIST] : DSO Selection | Sun Feb 06 2000 - 23:50:58 PST |
[email protected] |
| Re: [SI-LIST] : High Density Board to Board Connectors? | Mon Feb 14 2000 - 08:55:37 PST |
Marc Humphreys |
| RE: [SI-LIST] : board-level simulation for differential signals | Mon Apr 17 2000 - 06:35:54 PDT |
| RE: [SI-LIST] : board-level simulation for differential signals | Thu Apr 13 2000 - 11:56:28 PDT |
| RE: [SI-LIST] : receiver jitter | Tue Jan 18 2000 - 06:50:02 PST |
Mark Geddes |
| RE: [SI-LIST] : App note assumptions | Mon Apr 17 2000 - 07:53:57 PDT |
| RE: [SI-LIST] : Dielectric Material Comparison | Fri Apr 14 2000 - 15:32:21 PDT |
| [SI-LIST] : App note assumptions | Fri Apr 14 2000 - 12:31:34 PDT |
Mark Nass |
| RE: [SI-LIST] : Return path for stripline, two ground planes or one power and one ground? | Mon Apr 03 2000 - 12:05:32 PDT |
Mark Randol |
| Re: [SI-LIST] : Coax connection to a CPW guide | Fri Mar 31 2000 - 16:24:42 PST |
| Re: [SI-LIST] : Coplanar Transmission Line | Fri Feb 04 2000 - 16:39:08 PST |
| Re: [SI-LIST] : Another capacitor question | Thu Jan 27 2000 - 12:10:29 PST |
| Re: [SI-LIST] : What's your favourite Screwy SI Concept? | Mon Jan 10 2000 - 14:53:46 PST |
[email protected] |
| [SI-LIST] : RE: [SI-LIST] : �ظ�: [SI-LIST] : Parallel Plate Capacitance for Bypass | Fri Mar 31 2000 - 01:04:34 PST |
Marko Pulli |
| [SI-LIST] : PCB layout in pull up/down resistors | Wed Jan 26 2000 - 12:10:49 PST |
Martin thompson |
| RE: [SI-LIST] : Adding inductors to ground? | Fri Mar 03 2000 - 09:08:19 PST |
Mary |
| [SI-LIST] : 20-H Rule and Self-Resonant Frequency of Power Planes | Wed Apr 19 2000 - 09:45:12 PDT |
Matt (boomer) Russell |
| Re: [SI-LIST] : Clamp diodes in models (was Input switching threshold & CPCI) | Mon Jan 10 2000 - 11:20:34 PST |
| Re: [SI-LIST] : Input switching threshold & CPCI | Thu Jan 06 2000 - 11:36:57 PST |
Matt Kaufmann |
| [SI-LIST] : Summer intern position | Wed Apr 05 2000 - 14:36:24 PDT |
| [SI-LIST] : bandwidth saving question | Thu Feb 10 2000 - 14:42:51 PST |
Matthias Mansfeld |
| Re: [SI-LIST] : ACCEL's "signal integrity" tool | Thu Mar 02 2000 - 08:15:18 PST |
Mayer, Mike |
| RE: [SI-LIST] : SI FAQ Proposal | Thu Mar 23 2000 - 05:55:21 PST |
| RE: [SI-LIST] : Bad IBIS models! | Fri Mar 17 2000 - 12:46:38 PST |
| RE: [SI-LIST] : Fast edges with limited plane capacitance | Fri Mar 17 2000 - 11:11:55 PST |
| RE: [SI-LIST] : Bad IBIS models! | Thu Mar 16 2000 - 13:38:43 PST |
| RE: [SI-LIST] : Bad IBIS models! | Thu Mar 16 2000 - 12:43:46 PST |
| RE: [SI-LIST] : Bad IBIS models! | Wed Mar 15 2000 - 14:21:16 PST |
| [SI-LIST] : RE: [IS-LIST] : why .062? | Thu Mar 09 2000 - 06:27:03 PST |
| RE: [SI-LIST] : MPC860 IBIS model | Tue Mar 07 2000 - 10:16:36 PST |
| RE: [SI-LIST] : Adding inductors to ground? | Fri Mar 03 2000 - 05:48:38 PST |
| RE: [SI-LIST] : CAD for SI, EMC. Hyperlynx experiences. | Thu Feb 17 2000 - 13:35:27 PST |
| RE: [SI-LIST] : Anyone on SI-list receiving UCE type spam? | Fri Feb 11 2000 - 06:14:31 PST |
| [SI-LIST] : Training Suggestions Wanted | Tue Feb 08 2000 - 05:51:45 PST |
| RE: [SI-LIST] : Chassis hole opening and frequencies | Mon Jan 10 2000 - 11:05:55 PST |
| [SI-LIST] : DesignCon 2000 | Mon Jan 10 2000 - 11:04:23 PST |
[email protected] |
| RE: [SI-LIST] : Frequency or time domain for component characterization | Tue Feb 29 2000 - 03:31:41 PST |
| RE: [SI-LIST] : Hopefully not a controversial question ... | Thu Feb 24 2000 - 12:15:36 PST |
[email protected] |
| [SI-LIST] : Terminator location with larger BGA's | Fri Apr 07 2000 - 13:16:31 PDT |
Mellitz, Richard |
| RE: [SI-LIST] : Creating and displaying eye diagrams with Avanti HSpice..... | Thu Feb 17 2000 - 12:26:17 PST |
| [SI-LIST] :What do inputs do? monotonic signals at SDRAM-, SSRAM - and FEPROM-a dress inputs | Mon Feb 14 2000 - 19:45:21 PST |
| RE: [SI-LIST] : **error**: internal timestep too small | Thu Jan 20 2000 - 13:38:05 PST |
| RE: [SI-LIST] : **error**: internal timestep too small | Wed Jan 19 2000 - 16:26:14 PST |
| RE: [SI-LIST] : receiver jitter | Wed Jan 19 2000 - 13:17:45 PST |
Merav Kass |
| [SI-LIST] : IBIS question regards [Falling Waveform] / [Rising Waveform]. | Tue Apr 11 2000 - 12:35:28 PDT |
Michael Kurten |
| [SI-LIST] : Ibis question | Tue Feb 22 2000 - 02:11:19 PST |
Michael O'Shaughnessy |
| FW: [SI-LIST] : Training Suggestions Wanted | Tue Feb 29 2000 - 11:43:48 PST |
Michael Schmitt |
| Re: [SI-LIST] : App note assumptions | Mon Apr 17 2000 - 00:07:38 PDT |
Michael Vrbanac |
| Re: [SI-LIST] : What's your favorite Screwy SI Concept? | Sun Jan 16 2000 - 17:26:35 PST |
| Re: [SI-LIST] : 20H Revisited | Fri Jan 14 2000 - 20:35:45 PST |
| Re: [SI-LIST] : What's your favorite Screwy SI Concept? | Fri Jan 14 2000 - 13:50:21 PST |
| Re: [SI-LIST] : Simulations | Fri Jan 14 2000 - 12:55:57 PST |
| Re: [SI-LIST] : 20H Revisited | Fri Jan 14 2000 - 10:31:36 PST |
| Re: [SI-LIST] : 20H Revisited | Thu Jan 13 2000 - 13:59:22 PST |
| Re: [SI-LIST] : 20H Revisited | Thu Jan 13 2000 - 10:45:31 PST |
| Re: [SI-LIST] : 20H Revisited | Thu Jan 13 2000 - 10:34:41 PST |
| Re: [SI-LIST] : 20H Revisited | Thu Jan 13 2000 - 09:08:17 PST |
| Re: [SI-LIST] : What's your favorite Screwy SI Concept? | Wed Jan 12 2000 - 08:42:41 PST |
| [SI-LIST] : re: [SI-LIST]: What's your favorite Screwy SI Concept? | Tue Jan 11 2000 - 21:32:19 PST |
| Re: [SI-LIST] : What's your favorite Screwy SI Concept? | Tue Jan 11 2000 - 21:09:13 PST |
| Re: [SI-LIST] : What's your favourite Screwy SI Concept? | Mon Jan 10 2000 - 20:49:39 PST |
| Re: [SI-LIST] : Chassis hole opening and frequencies | Mon Jan 10 2000 - 17:16:06 PST |
| Re: [SI-LIST] : What's your favorite Screwy SI Concept? | Mon Jan 10 2000 - 11:34:26 PST |
| Re: [SI-LIST] : What's your favorite Screwy SI Concept? | Sun Jan 09 2000 - 15:18:39 PST |
| Re: [SI-LIST] : What's your favorite Screwy SI Concept? | Sat Jan 08 2000 - 19:36:14 PST |
| Re: [SI-LIST] : What's your favorite Screwy SI Concept? | Fri Jan 07 2000 - 15:32:11 PST |
| Re: [SI-LIST] : What's your favorite Screwy SI Concept? | Fri Jan 07 2000 - 12:34:55 PST |
Mike Jenkins |
| Re: [SI-LIST] : Question on propagation delay........ | Mon Apr 17 2000 - 14:26:26 PDT |
| Re: [SI-LIST] : HSPICE Start Up conditions | Wed Mar 22 2000 - 17:05:24 PST |
Mike LaBonte |
| Re: [SI-LIST] : meaning and value of C_comp | Wed Mar 22 2000 - 06:09:46 PST |
| Re: [SI-LIST] : Bad IBIS models! | Thu Mar 16 2000 - 05:43:01 PST |
| Re: [SI-LIST] : Bad IBIS models! | Thu Mar 16 2000 - 05:54:32 PST |
| Re: [SI-LIST] : Bad IBIS models! | Thu Mar 16 2000 - 05:29:21 PST |
| Re: [SI-LIST] : receiver jitter | Thu Jan 20 2000 - 05:55:19 PST |
Mike Mayer |
| Re: [SI-LIST] : Possible FAQ Topics | Thu Feb 03 2000 - 10:49:26 PST |
Mike Ventham |
| Re: [SI-LIST] : Field solver | Wed Apr 05 2000 - 09:01:40 PDT |
| Re: [SI-LIST] : Crosstalk graphs | Mon Mar 06 2000 - 06:17:05 PST |
Mikhail Matusov |
| Re: [SI-LIST] : ACCEL's "signal integrity" tool | Thu Mar 02 2000 - 06:45:02 PST |
[email protected] |
| Re: [SI-LIST] : 20-H Rule and Self-Resonant Frequency of Power Pl anes | Wed Apr 19 2000 - 15:49:25 PDT |
| Re: [SI-LIST] : Bulk Caps -> Inductor? -> Plane | Tue Apr 11 2000 - 14:35:12 PDT |
| Re: [SI-LIST] : 20-H Rule and Self-Resonant Frequency of Power Planes | Fri Mar 31 2000 - 16:19:29 PST |
| Re: [SI-LIST] : Parallel Plate Capacitance for Bypass | Tue Mar 28 2000 - 07:36:15 PST |
| Re: [SI-LIST] : SI Society Chapter | Mon Mar 20 2000 - 12:47:32 PST |
| Re: [SI-LIST] : Fast edges with limited plane capacitance | Sat Mar 18 2000 - 12:25:58 PST |
| Re: [SI-LIST] : Fun With Stackups again | Sat Mar 18 2000 - 09:43:51 PST |
| Re: [SI-LIST] : Fast edges with limited plane capacitance | Fri Mar 17 2000 - 11:21:51 PST |
| Re: [SI-LIST] : Fast edges with limited plane capacitance | Fri Mar 17 2000 - 10:51:38 PST |
| Re: [SI-LIST] : Fast edges with limited plane capacitance | Fri Mar 17 2000 - 10:25:52 PST |
| Re: [SI-LIST] : A basic question | Fri Mar 17 2000 - 09:27:42 PST |
| Re: [SI-LIST] : Hopefully not a controversial question ... | Thu Feb 24 2000 - 14:11:04 PST |
| Re: [SI-LIST] : Hopefully not a controversial question ... | Thu Feb 24 2000 - 11:57:54 PST |
mjs |
| RE: [SI-LIST] : Bulk Caps -> Inductor? -> Plane | Tue Apr 11 2000 - 15:01:06 PDT |
| [SI-LIST] : Bulk Caps -> Inductor? -> Plane | Tue Apr 11 2000 - 11:58:33 PDT |
| Re: [SI-LIST] : Fast edges with limited plane capacitance | Fri Mar 17 2000 - 13:54:24 PST |
| [SI-LIST] : Fast edges with limited plane capacitance | Fri Mar 17 2000 - 08:29:33 PST |
mmunroe |
| [SI-LIST] : High Speed Backplane Connector Recommendations | Thu Jan 13 2000 - 11:30:55 PST |
Muranyi, Arpad |
| [SI-LIST] : SI position at Intel Folsom, CA | Thu Apr 20 2000 - 11:12:59 PDT |
| RE: [SI-LIST] : HSPICE Vector File Problem | Mon Apr 17 2000 - 14:28:34 PDT |
| RE: [SI-LIST] : SI FAQ Proposal | Wed Mar 22 2000 - 17:11:57 PST |
| RE: [SI-LIST] : Bad IBIS models! | Fri Mar 17 2000 - 13:03:39 PST |
| RE: [SI-LIST] : Bad IBIS models! | Fri Mar 17 2000 - 11:07:45 PST |
| RE: [SI-LIST] : Bad IBIS models! | Fri Mar 17 2000 - 10:41:26 PST |
| RE: [SI-LIST] : Bad IBIS models! | Fri Mar 17 2000 - 10:32:08 PST |
| RE: [SI-LIST] : Bad IBIS models! | Fri Mar 17 2000 - 10:15:00 PST |
| RE: [SI-LIST] : Bad IBIS models! | Fri Mar 17 2000 - 10:07:57 PST |
| RE: [SI-LIST] : VTT supply | Mon Mar 13 2000 - 08:19:09 PST |
| RE: [SI-LIST] : modeling languages (was: receiver jitter) | Fri Feb 04 2000 - 13:24:38 PST |
| RE: [SI-LIST] : modeling languages (was: receiver jitter) | Fri Jan 21 2000 - 12:39:07 PST |
| RE: [SI-LIST] : modeling languages (was: receiver jitter) | Fri Jan 21 2000 - 11:59:36 PST |
| RE: [SI-LIST] : **error**: internal timestep too small | Fri Jan 21 2000 - 07:57:26 PST |
| RE: [SI-LIST] : modeling languages (was: receiver jitter) | Thu Jan 20 2000 - 17:35:26 PST |
| RE: [SI-LIST] : **error**: internal timestep too small | Thu Jan 20 2000 - 12:18:42 PST |
| RE: [SI-LIST] : **error**: internal timestep too small | Thu Jan 20 2000 - 08:54:39 PST |
| RE: [SI-LIST] : minor si-list problem resolved | Wed Jan 19 2000 - 08:43:42 PST |
| RE: [SI-LIST] : receiver jitter | Tue Jan 18 2000 - 08:23:07 PST |
| RE: [SI-LIST] : Clamp diodes in models (was Input switchingthresh old & CPCI) | Mon Jan 10 2000 - 11:37:04 PST |
| RE: [SI-LIST] : What's your favorite Screwy SI Concept? | Thu Jan 06 2000 - 12:46:53 PST |
Muzahid Huda |
| Re: [SI-LIST] : SI Society Chapter | Mon Mar 20 2000 - 11:25:26 PST |
Myra Torres |
| Re: [SI-LIST] : Bad IBIS models! - Business thoughts | Fri Mar 17 2000 - 16:12:54 PST |
Nadolny, Jim |
| RE: [SI-LIST] : 20-H Rule and Self-Resonant Frequency of Power Pl anes | Wed Apr 19 2000 - 11:05:34 PDT |
| RE: [SI-LIST] : Chassis hole opening and frequencies | Tue Jan 04 2000 - 10:47:16 PST |
Nerheim, Max |
| [SI-LIST] : SI Position available, Intel, Chandler - AZ | Wed Mar 29 2000 - 12:10:10 PST |
| RE: [SI-LIST] : Number of GND/Power pins in a connector ? | Mon Mar 27 2000 - 07:47:57 PST |
| RE: [SI-LIST] : Number of GND/Power pins in a connector ? | Fri Mar 24 2000 - 10:20:55 PST |
Netzler Dirk |
| AW: [SI-LIST] : different 4-layer board Stack up (S-P-G-S) ? | Tue Mar 07 2000 - 07:05:14 PST |
| [SI-LIST] : montonic signals at SDRAM-, SSRAM- and FEPROM-adress inputs | Thu Feb 10 2000 - 23:01:47 PST |
Neven Pischl |
| Re: [SI-LIST] : SI Society Chapter | Mon Mar 20 2000 - 09:42:12 PST |
| [SI-LIST] : Job Opening at Cisco in San Jose, CA - EMC Design Engineer | Wed Mar 15 2000 - 11:30:41 PST |
| RE: [SI-LIST] : What's your favourite Screwy SI Concept? | Fri Jan 14 2000 - 13:26:20 PST |
Nick Dietz |
| Re: [SI-LIST] : Bulk Caps -> Inductor? -> Plane | Tue Apr 11 2000 - 13:44:34 PDT |
| [SI-LIST] : Gigabit eithernet board. | Fri Feb 04 2000 - 09:47:55 PST |
[email protected] |
| [SI-LIST] : routing problems | Thu Apr 06 2000 - 16:42:37 PDT |
Nirmal Jain |
| Re: [SI-LIST] : different 4-layer board Stack up (S-P-G-S) ? | Tue Mar 07 2000 - 13:58:46 PST |
| Re: [SI-LIST] : width of the return path | Sun Jan 16 2000 - 11:38:15 PST |
| Re: [SI-LIST] : backward Xtalk? | Mon Jan 10 2000 - 17:33:02 PST |
| Re:[SI-LIST] : questions about Spicelink/Ansoft tools | Mon Jan 10 2000 - 11:32:40 PST |
Norbert Seitz |
| Re: [SI-LIST] : Field solver | Tue Apr 04 2000 - 15:46:03 PDT |
| [SI-LIST] : In search of other lists. | Tue Mar 21 2000 - 11:44:29 PST |
| Re: [SI-LIST] : Software scope, VOM | Mon Mar 13 2000 - 10:38:40 PST |
Norman Ebsary |
| RE: [SI-LIST] : Dielectric Material Comparison | Mon Apr 17 2000 - 13:16:56 PDT |
Ooi, Thien Ern |
| RE: [SI-LIST] : tracking/oversampling PLL architectures | Fri Mar 10 2000 - 17:29:09 PST |
| [SI-LIST] : tracking/oversampling PLL architectures | Wed Mar 08 2000 - 18:58:32 PST |
[email protected] |
| FW: [SI-LIST] : Looking for shielded Din 41612 compatible connector | Wed Feb 02 2000 - 09:43:23 PST |
[email protected] |
| [SI-LIST] : What's your favorite Screwy SI Concept? : low ESR decoupling capacitors | Wed Jan 05 2000 - 15:48:34 PST |
P.R.Dewasthalee |
| RE: [SI-LIST] : SPICE models for LVDS and LVPECL | Sun Mar 26 2000 - 05:39:03 PST |
Patrick Lawler |
| Re: [SI-LIST] : Excessive Posting Length | Mon Jan 17 2000 - 08:51:17 PST |
Patterson, Ken |
| RE: [SI-LIST] : PLL clock buffer chips and the feedback loop | Mon Apr 03 2000 - 11:35:01 PDT |
| RE: [SI-LIST] : SI Society Chapter | Mon Mar 20 2000 - 11:51:49 PST |
| RE: [SI-LIST] : Info about Xilinx Xchecker Cables | Thu Feb 03 2000 - 12:12:27 PST |
Paul Thompson |
| Re: [SI-LIST] : Fast edges with limited plane capacitance | Fri Mar 17 2000 - 15:11:23 PST |
[email protected] |
| RE: [SI-LIST] : Opinions on SI CAE tools | Fri Feb 25 2000 - 18:48:26 PST |
Peter Baxter |
| [SI-LIST] : Printer Port | Sun Apr 09 2000 - 15:23:25 PDT |
| [SI-LIST] : Max Zo of Flat Flexible Cable | Sat Feb 26 2000 - 13:54:43 PST |
Peter Luu |
| Re: [SI-LIST] : a good SI/Layout book | Thu Apr 06 2000 - 12:29:57 PDT |
Peters, Stephen |
| RE: [SI-LIST] : anybody fielding newbie questions?? | Mon Apr 17 2000 - 13:52:06 PDT |
| RE: [SI-LIST] : IBIS question regards [Falling Waveform] / [Risin g Waveform]. | Tue Apr 11 2000 - 15:13:42 PDT |
| RE: [SI-LIST] : PLL clock buffer chips and the feedback loop | Thu Apr 06 2000 - 14:16:21 PDT |
| RE: [SI-LIST] : SI Society Chapter | Mon Mar 20 2000 - 12:24:02 PST |
| RE: [SI-LIST] : Spice to IBIS Converter | Mon Mar 20 2000 - 08:32:15 PST |
| [SI-LIST] : Anyone on SI-list receiving UCE type spam? | Thu Feb 10 2000 - 17:28:25 PST |
Peterson, George W |
| [SI-LIST] : HSplot | Thu Mar 02 2000 - 09:16:29 PST |
Peterson, James F (FL51) |
| RE: [SI-LIST] : Signal Integrity Position | Mon Apr 03 2000 - 05:42:51 PDT |
| FW: [SI-LIST] : A basic question | Fri Mar 17 2000 - 09:39:12 PST |
| RE: [SI-LIST] : A basic question | Fri Mar 17 2000 - 05:51:24 PST |
| [SI-LIST] : A basic question | Fri Mar 17 2000 - 05:00:49 PST |
| RE: [SI-LIST] : A basic question | Fri Mar 17 2000 - 05:53:59 PST |
| [SI-LIST] : job opportunity | Thu Mar 09 2000 - 04:53:04 PST |
| RE: [SI-LIST] : Fast edge termination choice | Sat Feb 26 2000 - 07:42:16 PST |
| RE: [SI-LIST] : monotonic signals at SDRAM-, SSRAM- and FEPROM-a dress inputs | Wed Feb 16 2000 - 12:44:39 PST |
| RE: [SI-LIST] : monotonic signals at SDRAM-, SSRAM- and FEPROM-a dress inputs | Mon Feb 14 2000 - 08:11:03 PST |
| RE: [SI-LIST] : Power Plane for Internal Device Power? | Fri Jan 28 2000 - 04:19:58 PST |
| RE: [SI-LIST] : Decoupling capacitor resonance | Wed Jan 26 2000 - 05:38:20 PST |
| RE: [SI-LIST] : Input switching threshold & CPCI | Tue Jan 04 2000 - 11:09:56 PST |
phelan, tony |
| [SI-LIST] : Power Plane for Internal Device Power? | Thu Jan 27 2000 - 11:35:46 PST |
[email protected] |
| Re: [SI-LIST] : EMC techniques on 2-layer board | Fri Feb 04 2000 - 08:06:51 PST |
[email protected] |
| Re: [SI-LIST] : SI Society Chapter | Mon Mar 20 2000 - 09:59:20 PST |
PRDEWASTHALEE |
| RE: [SI-LIST] : What's your favorite Screwy SI Concept? | Mon Jan 10 2000 - 11:20:17 PST |
qzhao |
| [SI-LIST] : Job opening at Cisco | Thu Mar 09 2000 - 14:58:57 PST |
rachild.chen |
| [SI-LIST] : �ظ�: [SI-LIST] : Parallel Plate Capacitance for Bypass | Thu Mar 30 2000 - 19:43:45 PST |
| [SI-LIST] : �ظ�: [SI-LIST] : SI Society Chapte | Thu Mar 23 2000 - 23:39:57 PST |
| [SI-LIST] : Now SI Engineer job positions is in Shenzhen China | Fri Mar 10 2000 - 01:36:11 PST |
| [SI-LIST] : Sorry for HMTL/SOS for CPCI | Thu Mar 09 2000 - 17:07:33 PST |
| [SI-LIST] : Where can I get some design informations about CPCI? | Wed Mar 08 2000 - 19:31:14 PST |
| [SI-LIST] : �ظ�: [SI-LIST] : A excellent SI Enginer position in Chin | Mon Feb 28 2000 - 22:22:30 PST |
| [SI-LIST] : A excellent SI Engineer position in China | Mon Feb 28 2000 - 17:26:56 PST |
| �ظ�: [SI-LIST] : Power / Ground simulation | Fri Feb 18 2000 - 00:24:31 PST |
ramesh srinivasan |
| [SI-LIST] : Differential LVPECL termination | Thu Mar 30 2000 - 01:59:21 PST |
Ravinder Ajmani |
| RE: [SI-LIST] : FCAL DB9 cable shield | Mon Jan 10 2000 - 13:20:47 PST |
Ray Anderson |
| Re: [SI-LIST] : 20-H Rule and Self-Resonant Frequency of Power Planes | Thu Apr 20 2000 - 11:06:20 PDT |
| Re: [SI-LIST] : Friendly reminder about message formatting | Wed Apr 19 2000 - 12:21:27 PDT |
| Re: [SI-LIST] : App note assumptions | Fri Apr 14 2000 - 13:05:08 PDT |
| [SI-LIST] : 20-H Rule disclosure | Thu Apr 13 2000 - 11:58:44 PDT |
| [SI-LIST] : ViPEC (Touchstone QPL clone) | Fri Apr 07 2000 - 10:13:27 PDT |
| Re: [SI-LIST] : a good SI/Layout book | Thu Apr 06 2000 - 12:26:38 PDT |
| Re: Fw: [SI-LIST] : via capacitance | Tue Mar 28 2000 - 00:17:53 PST |
| Re: [SI-LIST] : Parallel Plate Capacitance for Bypass | Fri Mar 24 2000 - 15:13:56 PST |
| Re: [SI-LIST] : Parallel Plate Capacitance for Bypass | Fri Mar 24 2000 - 14:46:54 PST |
| [SI-LIST] : IEEE SI Chapter Action Update | Sat Mar 18 2000 - 12:50:14 PST |
| Re: [SI-LIST] : SI FAQ Proposal | Wed Mar 22 2000 - 10:36:06 PST |
| [SI-LIST] : SI FAQ Proposal | Tue Mar 21 2000 - 16:17:01 PST |
| [SI-LIST] : How to create IEEE SI Society Chapters ? | Mon Mar 20 2000 - 13:11:54 PST |
| RE: [SI-LIST] : SI Society Chapter | Mon Mar 20 2000 - 12:13:05 PST |
| [SI-LIST] : EPEP 2000 Call For Papers | Sun Mar 12 2000 - 11:16:32 PST |
| Re: [SI-LIST] : ribbon cable models | Thu Mar 09 2000 - 14:23:45 PST |
| Re: [SI-LIST] : Your experience with equivalent circuit modeling tools ... | Thu Mar 09 2000 - 14:14:19 PST |
| [SI-LIST] : Posting from multiple account addresses | Tue Mar 07 2000 - 10:27:31 PST |
| RE: [SI-LIST] : Adding inductors to ground? | Fri Mar 03 2000 - 12:22:47 PST |
| RE: [SI-LIST] : Adding inductors to ground? | Thu Mar 02 2000 - 11:12:22 PST |
| [SI-LIST] : spice directional coupler model | Wed Mar 01 2000 - 14:38:31 PST |
| Re: [SI-LIST] : Frequency or time domain for component characterization | Mon Feb 28 2000 - 13:20:02 PST |
| Re: [SI-LIST] : Re: Opportunities | Mon Feb 28 2000 - 11:43:13 PST |
| Re: [SI-LIST] : Re: Opportunities | Wed Feb 23 2000 - 03:55:58 PST |
| Re: [SI-LIST] : Bulk Capacitance | Fri Feb 25 2000 - 11:08:01 PST |
| Re: [SI-LIST] : stripline PCB board shrinkage? | Wed Feb 23 2000 - 13:27:46 PST |
| RE: [SI-LIST] : Creating and displaying eye diagrams with Avanti HSpice..... | Thu Feb 17 2000 - 13:25:10 PST |
| Re: [SI-LIST] : Creating and displaying eye diagrams with Avanti HSpice..... | Thu Feb 17 2000 - 12:18:58 PST |
| RE: [SI-LIST] : ESR and bypass caps | Wed Feb 16 2000 - 14:52:24 PST |
| [SI-LIST] : si-list subscriber demographics | Thu Feb 10 2000 - 14:48:40 PST |
| Re: [SI-LIST] : ESR and bypass caps | Mon Feb 07 2000 - 16:58:17 PST |
| Re: [SI-LIST] : ESR and bypass caps | Wed Jan 12 2000 - 15:54:46 PST |
| Re: [SI-LIST] : ESR and bypass caps | Fri Feb 04 2000 - 13:28:44 PST |
| Re: [SI-LIST] : ESR and bypass caps | Fri Feb 04 2000 - 12:40:05 PST |
| [SI-LIST] : Oooops.... | Fri Feb 04 2000 - 09:54:52 PST |
| Re: [SI-LIST] : Coplanar Transmission Line | Thu Feb 03 2000 - 13:05:06 PST |
| Re: [SI-LIST] : Coplanar Transmission Line | Thu Feb 03 2000 - 12:52:23 PST |
| Re: [SI-LIST] : interplanar capacitance | Thu Feb 03 2000 - 12:27:36 PST |
| Re: [SI-LIST] : Coplanar Transmission Line | Thu Feb 03 2000 - 11:34:49 PST |
| [SI-LIST] : Possible FAQ Topics | Wed Jan 12 2000 - 13:16:32 PST |
| [SI-LIST] : si-list FAQ | Wed Feb 02 2000 - 13:25:55 PST |
| [SI-LIST] : Announcement and Call for Papers (EPEP '00) | Fri Jan 28 2000 - 15:13:28 PST |
| Re: [SI-LIST] : Questions abt Power Distribution System | Fri Jan 28 2000 - 10:41:14 PST |
| Re: [SI-LIST] : Another capacitor question | Thu Jan 27 2000 - 11:46:48 PST |
| Re: [SI-LIST] : Another capacitor question | Thu Jan 27 2000 - 10:33:32 PST |
| Re: [SI-LIST] : Decoupling capacitor resonance | Wed Jan 12 2000 - 05:59:50 PST |
| Re: [SI-LIST] : Another capacitor question | Wed Jan 26 2000 - 13:28:50 PST |
| Re: [SI-LIST] : Decoupling capacitor resonance | Wed Jan 26 2000 - 10:27:49 PST |
| [SI-LIST] : New Experimental si-list-digest service | Wed Jan 19 2000 - 11:46:17 PST |
| [SI-LIST] : minor si-list problem resolved | Tue Jan 18 2000 - 14:45:45 PST |
| Re: [SI-LIST] : 20H Revisited | Thu Jan 13 2000 - 10:15:59 PST |
| [SI-LIST] : message foul-up | Mon Jan 10 2000 - 12:02:39 PST |
| [SI-LIST] : si-list archives | Sat Jan 08 2000 - 13:20:28 PST |
Ray Waugh |
| RE: [SI-LIST] : Coax connection to a CPW guide | Fri Mar 31 2000 - 15:29:53 PST |
| RE: [SI-LIST] : Chassis hole opening and frequencies | Mon Jan 10 2000 - 11:08:35 PST |
[email protected] |
| Re: [SI-LIST] : SSC | Wed Mar 15 2000 - 19:20:15 PST |
| Re: [SI-LIST] : SSC | Tue Mar 14 2000 - 15:14:49 PST |
| Re: [SI-LIST] : LVDS driving PCML | Wed Mar 08 2000 - 20:44:08 PST |
| [SI-LIST] : differential trace model (was: receiver jitter) | Wed Jan 19 2000 - 20:45:08 PST |
| Re: [SI-LIST] : High Speed Backplane Connector Recommendations | Sun Jan 16 2000 - 16:21:22 PST |
rbishop |
| Re: [SI-LIST] : why .062? | Thu Mar 09 2000 - 07:32:44 PST |
[email protected] |
| Re: [SI-LIST] : 20-H Rule and Self-Resonant Frequency of Power Pl anes | Thu Apr 20 2000 - 10:33:01 PDT |
| RE: [SI-LIST] : A basic question | Fri Mar 17 2000 - 08:15:07 PST |
| Re: [SI-LIST] : ESR and bypass caps | Mon Feb 07 2000 - 06:22:07 PST |
| Re: [SI-LIST] : What's your favorite Screwy SI Concept? | Wed Jan 12 2000 - 06:25:06 PST |
| Re: [SI-LIST] : What's your favourite Screwy SI Concept? | Wed Jan 05 2000 - 08:32:16 PST |
Rehm, Dennis |
| [SI-LIST] : ribbon cable models | Thu Mar 09 2000 - 14:06:52 PST |
Rengarajan S Krishnan |
| Re: [SI-LIST] : PLL clock buffer chips and the feedback loop | Fri Apr 07 2000 - 09:11:09 PDT |
Richard A. Schumacher |
| [SI-LIST] : Friendly reminder about message formatting | Wed Apr 19 2000 - 11:58:14 PDT |
| Re: [SI-LIST] : ESR and bypass caps | Fri Feb 04 2000 - 15:43:03 PST |
| [SI-LIST] : C and L measurements using a TDR | Fri Jan 14 2000 - 14:48:17 PST |
| RE: [SI-LIST] : What's your favorite Screwy SI Concept? | Tue Jan 11 2000 - 16:55:06 PST |
Richard G. Munden |
| Re: [SI-LIST] : Bad IBIS models! | Thu Mar 16 2000 - 21:43:15 PST |
Richard Kuo |
| Re: [SI-LIST] : Searching XTK utils. | Wed Feb 23 2000 - 17:13:26 PST |
Rick Brooks |
| Re: [SI-LIST] : Number of GND/Power pins in a connector ? | Mon Mar 27 2000 - 07:44:00 PST |
Ritchey Lee |
| Re: Fw: [SI-LIST] : via capacitance | Mon Apr 10 2000 - 09:21:14 PDT |
| Re: [SI-LIST] : via capacitance | Mon Apr 10 2000 - 09:15:36 PDT |
| Re: [SI-LIST] : �ظ�: [SI-LIST] : Parallel Plate Capacitance for Bypass | Mon Apr 10 2000 - 09:13:04 PDT |
| Re: [SI-LIST] : SI FAQ Proposal | Thu Mar 23 2000 - 09:25:49 PST |
| Re: [SI-LIST] : trace width for clock routing- wider/narrower? | Mon Mar 13 2000 - 08:05:36 PST |
| Re: [SI-LIST] :PCB Bd thkness' | Fri Mar 10 2000 - 08:02:47 PST |
| Re: [SI-LIST] : Adding inductors to ground? | Fri Mar 03 2000 - 16:50:44 PST |
| Re: [SI-LIST] : Islands of Power | Fri Mar 03 2000 - 16:46:15 PST |
| Re: [SI-LIST] : ACCEL's "signal integrity" tool | Fri Mar 03 2000 - 16:08:44 PST |
| Re: [SI-LIST] : Crosstalk graphs | Fri Mar 03 2000 - 16:07:50 PST |
| Re: [SI-LIST] : Adding inductors to ground? | Thu Mar 02 2000 - 17:46:33 PST |
Robert Stuart |
| [SI-LIST] : Any buffer suggestions? | Sat Mar 25 2000 - 00:12:27 PST |
Roberts, Chris |
| [SI-LIST] : Signal Integrity simulation tools | Wed Feb 02 2000 - 05:34:06 PST |
Robison Michael R CNIN |
| [SI-LIST] : anybody fielding newbie questions?? | Mon Apr 17 2000 - 13:13:01 PDT |
Ron Miller |
| RE: [SI-LIST] : via capacitance | Mon Apr 10 2000 - 13:40:27 PDT |
| RE: [SI-LIST] : Terminator location with larger BGA's | Fri Apr 07 2000 - 15:34:41 PDT |
| Re: [SI-LIST] : Parallel Plate Capacitance for Bypass | Mon Mar 27 2000 - 19:32:34 PST |
| Re: [SI-LIST] : Parallel Plate Capacitance for Bypass | Mon Mar 27 2000 - 10:39:10 PST |
| Re: [SI-LIST] : Parallel Plate Capacitance for Bypass | Fri Mar 24 2000 - 14:30:22 PST |
| Re: [SI-LIST] : Fast edges with limited plane capacitance | Fri Mar 17 2000 - 11:18:42 PST |
| Re: [SI-LIST] : Fast edges with limited plane capacitance | Fri Mar 17 2000 - 11:13:44 PST |
| Re: [SI-LIST] : How to measure differential pattern on testcoupon? | Thu Mar 02 2000 - 16:07:52 PST |
| Re: [SI-LIST] : Frequency or time domain for componentcharacterization | Mon Feb 28 2000 - 16:54:58 PST |
| Re: [SI-LIST] : Max Zo of Flat Flexible Cable | Mon Feb 28 2000 - 11:27:28 PST |
| [SI-LIST] : Re: Opportunities | Fri Feb 25 2000 - 15:42:34 PST |
| [SI-LIST] : Opportunities | Fri Feb 25 2000 - 11:49:45 PST |
| Re: [SI-LIST] : DSO Selection | Mon Feb 07 2000 - 12:00:41 PST |
| Re: [SI-LIST] : Power noise/ground bounce software | Fri Feb 04 2000 - 13:18:38 PST |
| Re: [SI-LIST] : ESR and bypass caps | Fri Feb 04 2000 - 11:43:31 PST |
| Re: [SI-LIST] : Coplanar Transmission Line | Thu Feb 03 2000 - 18:01:33 PST |
| Re: [SI-LIST] : Coplanar Transmission Line | Thu Feb 03 2000 - 17:51:53 PST |
| Re: [SI-LIST] : Another capacitor question | Thu Jan 27 2000 - 09:57:56 PST |
| Re: [SI-LIST] : Decoupling capacitor resonance | Wed Jan 26 2000 - 10:56:26 PST |
| Re: [SI-LIST] : Decoupling capacitor resonance | Tue Jan 25 2000 - 18:10:12 PST |
| Re: [SI-LIST] : 10 layer board stackup | Thu Jan 20 2000 - 14:43:13 PST |
| [SI-LIST] : [Fwd: TDNACal access] | Mon Jan 17 2000 - 17:19:58 PST |
| Re: [SI-LIST] : High Speed Backplane Connector Recommendations | Fri Jan 14 2000 - 16:40:46 PST |
| Re: [SI-LIST] : High Speed Backplane Connector Recommendations | Fri Jan 14 2000 - 10:34:57 PST |
| Re: [SI-LIST] : What's your favorite Screwy SI Concept? | Thu Jan 13 2000 - 18:15:29 PST |
| Re: [SI-LIST] : High Speed Backplane Connector Recommendations | Thu Jan 13 2000 - 17:12:46 PST |
| Re: [SI-LIST] : DesignCon 2000 | Mon Jan 10 2000 - 12:11:33 PST |
| Re: [SI-LIST] : Chassis hole opening and frequencies | Tue Jan 04 2000 - 12:22:14 PST |
Ron Mosher |
| [SI-LIST] : Signal integrity engineers | Fri Jan 14 2000 - 09:28:55 PST |
Ronald E. Nikel |
| RE: [SI-LIST] : Stack up | Thu Feb 24 2000 - 11:21:56 PST |
Ronald Miller |
| Re: [SI-LIST] : Max Zo of Flat Flexible Cable | Sat Feb 26 2000 - 18:55:00 PST |
Ronnen Lovinger |
| [SI-LIST] : IBIS for SSTL_2 | Mon Apr 17 2000 - 08:31:46 PDT |
| [SI-LIST] :PECL spec? | Wed Jan 26 2000 - 02:33:50 PST |
Roy Leventhal |
| Re: [SI-LIST] : Signal Integrity Position | Fri Mar 31 2000 - 05:33:34 PST |
| Re: [SI-LIST] : SI Society Chapter | Mon Mar 20 2000 - 15:35:35 PST |
| Re: [SI-LIST] : Bad IBIS models! | Thu Mar 16 2000 - 07:05:20 PST |
| Re: [SI-LIST] : Bad IBIS models! | Thu Mar 16 2000 - 13:25:34 PST |
| Re: [SI-LIST] : Bad IBIS models! | Wed Mar 15 2000 - 13:55:00 PST |
| Re: [SI-LIST] : Bad IBIS models! | Wed Mar 15 2000 - 14:43:26 PST |
| Re: [SI-LIST] : Bad IBIS models! | Wed Mar 15 2000 - 14:38:16 PST |
| Re: [SI-LIST] : Bad IBIS models! | Wed Mar 15 2000 - 14:35:27 PST |
| [SI-LIST] : Crosstalk graphs | Thu Feb 24 2000 - 12:28:48 PST |
| Re: [SI-LIST] : High Speed Design by Rules of Thumb vs. Simulation | Mon Feb 21 2000 - 07:56:53 PST |
| Re: [SI-LIST] : DesignCon20000 paper posted | Mon Feb 07 2000 - 06:27:38 PST |
| RE: [SI-LIST] : Coplanar Transmission Line | Fri Feb 04 2000 - 10:24:25 PST |
| RE: [SI-LIST] : Coplanar Transmission Line | Fri Feb 04 2000 - 09:05:45 PST |
| Re: [SI-LIST] : Coplanar Transmission Line | Fri Feb 04 2000 - 07:11:41 PST |
| Re: [SI-LIST] : Coplanar Transmission Line | Fri Feb 04 2000 - 06:03:06 PST |
| Re: [SI-LIST] : Coplanar Transmission Line | Thu Feb 03 2000 - 14:20:11 PST |
| Re: [SI-LIST] : Coplanar Transmission Line | Thu Feb 03 2000 - 11:55:31 PST |
| RE: [SI-LIST] : Coplanar Transmission Line | Thu Feb 03 2000 - 11:49:43 PST |
| [SI-LIST] : Coplanar Transmission Line | Thu Feb 03 2000 - 10:58:26 PST |
| Re: [SI-LIST] : Decoupling capacitor resonance | Wed Jan 26 2000 - 12:00:18 PST |
| Re: [SI-LIST] : Decoupling capacitor resonance | Wed Jan 26 2000 - 07:29:40 PST |
| RE: [SI-LIST] : receiver jitter | Tue Jan 18 2000 - 15:02:54 PST |
S Weir |
| Re: [SI-LIST] : SpectraQuest vs XTK | Tue Mar 07 2000 - 10:46:58 PST |
S. Weir |
| RE: [SI-LIST] : AC Coupling vs DC Coupling | Mon Apr 17 2000 - 14:35:16 PDT |
| Re: [SI-LIST] : App note assumptions | Sat Apr 15 2000 - 00:55:13 PDT |
| Re: [SI-LIST] : Printer Port | Sun Apr 09 2000 - 18:11:37 PDT |
| RE: [SI-LIST] : Parallel Plate Capacitance for Bypass | Mon Mar 27 2000 - 12:01:18 PST |
| Re: [SI-LIST] : Number of GND/Power pins in a connector ? | Sat Mar 25 2000 - 15:52:18 PST |
| Re: [SI-LIST] : Any buffer suggestions? | Sat Mar 25 2000 - 15:45:55 PST |
| Re: [SI-LIST] : Parallel Plate Capacitance for Bypass | Fri Mar 24 2000 - 18:48:55 PST |
| Re: [SI-LIST] : Parallel Plate Capacitance for Bypass | Fri Mar 24 2000 - 18:41:09 PST |
| Re: [SI-LIST] : Number of GND/Power pins in a connector ? | Fri Mar 24 2000 - 18:35:40 PST |
| RE: [SI-LIST] : SI Society Chapter | Mon Mar 20 2000 - 13:35:48 PST |
| Re: [SI-LIST] : Catching the Corners: chain of synchronizingregisters | Mon Mar 20 2000 - 12:51:16 PST |
| Re: [SI-LIST] : Daisy-Chain | Mon Mar 20 2000 - 12:44:52 PST |
| Re: [SI-LIST] : Daisy-Chain | Mon Mar 20 2000 - 00:47:45 PST |
| Re: [SI-LIST] : Fast edges with limited plane capacitance | Sun Mar 19 2000 - 03:00:55 PST |
| Re: [SI-LIST] : Catching the Corners: chain of synchronizing registers | Sun Mar 19 2000 - 02:41:15 PST |
| RE: [SI-LIST] : trace width for clock routing- wider/narrower? | Mon Mar 13 2000 - 00:43:33 PST |
| Re: [SI-LIST] : VTT supply | Mon Mar 13 2000 - 00:21:22 PST |
| Re: [SI-LIST] : trace width for clock routing- wider/narrower? | Sun Mar 12 2000 - 17:29:08 PST |
| RE: [SI-LIST] : Adding inductors to ground? | Sat Mar 04 2000 - 04:16:06 PST |
| Re: [SI-LIST] : Islands of Power | Sat Mar 04 2000 - 04:05:53 PST |
| RE: [SI-LIST] : High Speed Design by Rules of Thumb vs. Simulation | Sun Feb 20 2000 - 21:38:36 PST |
| Re: [SI-LIST] : measuring radiation | Sat Feb 19 2000 - 13:40:56 PST |
| Re: [SI-LIST] : High Speed Design by Rules of Thumb vs. Simulation | Sat Feb 19 2000 - 14:18:45 PST |
Sage Gunderson |
| [SI-LIST] : Anyone interested in Howard's book (will trade for Poon's book) | Tue Feb 22 2000 - 13:46:09 PST |
Sainath Nimmagadda |
| Re: [SI-LIST] : si-list FAQ | Wed Feb 02 2000 - 14:06:35 PST |
| Re: [SI-LIST] : 20H Revisited | Fri Jan 14 2000 - 17:34:03 PST |
| Re: [SI-LIST] : 20H Revisited | Thu Jan 13 2000 - 16:19:16 PST |
| Re: [SI-LIST] : 20H Revisited | Thu Jan 13 2000 - 11:45:09 PST |
| Re: [SI-LIST] : 20H Revisited | Thu Jan 13 2000 - 09:40:34 PST |
Salvador Aguinaga |
| [SI-LIST] : Other ways of transmitting differential signalling besides edge coupled traces or broad side coupled traces | Thu Feb 17 2000 - 16:29:32 PST |
[email protected] |
| RE: [SI-LIST] : SI Society Chapter | Mon Mar 20 2000 - 21:47:58 PST |
| RE: [SI-LIST] : DSO Selection | Tue Feb 08 2000 - 19:56:15 PST |
| RE: [SI-LIST] : Coplanar Transmission Line | Thu Feb 03 2000 - 18:24:34 PST |
Sandy Taylor |
| [SI-LIST] : on-chip decoupling capacitance (and SI) | Tue Apr 18 2000 - 16:29:03 PDT |
[email protected] |
| [SI-LIST] : digital display interface | Thu Apr 13 2000 - 08:19:42 PDT |
| [SI-LIST] : LVDS drive LCD | Tue Feb 29 2000 - 05:19:46 PST |
Scott Brenneman |
| RE: [SI-LIST] :PCB Bd thkness' | Tue Mar 07 2000 - 15:09:59 PST |
| RE: [SI-LIST] : SpectraQuest vs XTK | Tue Mar 07 2000 - 15:12:28 PST |
| RE: [SI-LIST] : Where for art thou Tantalum Caps? | Thu Feb 17 2000 - 15:45:15 PST |
Scott McMorrow |
| Re: [SI-LIST] : AC Coupling vs DC Coupling | Mon Apr 17 2000 - 14:36:36 PDT |
| Re: [SI-LIST] : IBIS for SSTL_2 | Mon Apr 17 2000 - 10:36:31 PDT |
| Re: [SI-LIST] : AC Coupling vs DC Coupling | Mon Apr 17 2000 - 10:31:08 PDT |
| Re: [SI-LIST] : 20-H Rule and Self-Resonant Frequency of Power Planes | Thu Apr 13 2000 - 10:48:15 PDT |
| Re: [SI-LIST] : via capacitance | Tue Apr 11 2000 - 08:00:45 PDT |
| Re: [SI-LIST] : Terminator location with larger BGA's | Sat Apr 08 2000 - 23:42:36 PDT |
| Re: [SI-LIST] : Terminator location with larger BGA's | Fri Apr 07 2000 - 18:51:35 PDT |
| Re: [SI-LIST] : Terminator location with larger BGA's | Fri Apr 07 2000 - 18:00:22 PDT |
| Re: [SI-LIST] : Terminator location with larger BGA's | Fri Apr 07 2000 - 16:24:20 PDT |
| Re: [SI-LIST] : [SI-LIST] SI tools | Wed Apr 05 2000 - 14:23:35 PDT |
| Re: [SI-LIST] : Return path for stripline, two ground planesor one power and one ground? | Mon Apr 03 2000 - 14:01:37 PDT |
| Re: [SI-LIST] : Number of GND/Power pins in a connector ? | Thu Mar 23 2000 - 10:55:34 PST |
| Re: [SI-LIST] : Bad IBIS models! | Wed Mar 15 2000 - 14:03:22 PST |
| Re: [SI-LIST] : Bad IBIS models! | Wed Mar 15 2000 - 14:09:17 PST |
| Re: [SI-LIST] : trace width for clock routing- wider/narrower? | Mon Mar 13 2000 - 11:27:31 PST |
| Re: [SI-LIST] :PCB Bd thkness' | Tue Mar 07 2000 - 14:35:18 PST |
| Re: [SI-LIST] : MPC860 IBIS model | Tue Mar 07 2000 - 11:04:42 PST |
| Re: [SI-LIST] : Adding inductors to ground? | Wed Mar 01 2000 - 16:15:24 PST |
| Re: [SI-LIST] : Frequency or time domain for component characterization | Tue Feb 29 2000 - 10:41:12 PST |
| Re: [SI-LIST] : Frequency or time domain for component characterization | Tue Feb 29 2000 - 08:55:07 PST |
| Re: [SI-LIST] : (urgent) SI tool demand | Tue Feb 29 2000 - 00:34:09 PST |
| Re: [SI-LIST] : Frequency or time domain for component characterization | Mon Feb 28 2000 - 19:47:26 PST |
| Re: [SI-LIST] : Max Zo of Flat Flexible Cable | Sat Feb 26 2000 - 14:51:09 PST |
| Re: [SI-LIST] : Re: Opportunities | Fri Feb 25 2000 - 17:13:55 PST |
| Re: [SI-LIST] : Stack up | Wed Feb 23 2000 - 10:23:57 PST |
| Re: [SI-LIST] : High Speed Design by Rules of Thumb vs. Simulation | Mon Feb 21 2000 - 12:08:58 PST |
| Re: [SI-LIST] : High Speed Design by Rules of Thumb vs. Simulation | Sun Feb 20 2000 - 23:48:29 PST |
| Re: [SI-LIST] : Creating and displaying eye diagrams with Avanti HSpice..... | Thu Feb 17 2000 - 12:49:33 PST |
| Re: [SI-LIST] : Creating and displaying eye diagrams with Avanti HSpice..... | Thu Feb 17 2000 - 11:53:43 PST |
| Re: [SI-LIST] : monotonic signals at SDRAM-, SSRAM- and FEPROM-adress inputs | Mon Feb 14 2000 - 08:48:39 PST |
| Re: [SI-LIST] : montonic signals at SDRAM-, SSRAM- and FEPROM-adress inputs | Sat Feb 12 2000 - 01:08:35 PST |
| Re: [SI-LIST] : 10 layer board stackup Revisited | Wed Feb 09 2000 - 08:42:28 PST |
| Re: [SI-LIST] : DesignCon20000 paper posted | Mon Feb 07 2000 - 11:19:07 PST |
| Re: [SI-LIST] : ESR and bypass caps | Sun Feb 06 2000 - 22:15:43 PST |
| Re: [SI-LIST] : Coplanar Transmission Line | Thu Feb 03 2000 - 18:22:22 PST |
| Re: [SI-LIST] : Power Plane for Internal Device Power? | Thu Jan 27 2000 - 12:03:47 PST |
| Re: [SI-LIST] : receiver jitter | Wed Jan 19 2000 - 10:50:04 PST |
| Re: [SI-LIST] : XTK vs ICX | Wed Jan 19 2000 - 10:28:35 PST |
| Re: [SI-LIST] : What's your favourite Screwy SI Concept? | Sat Jan 15 2000 - 12:36:30 PST |
| Re: [SI-LIST] : What's your favourite Screwy SI Concept? | Sat Jan 15 2000 - 12:33:43 PST |
| Re: [SI-LIST] : Simulations | Fri Jan 14 2000 - 13:53:06 PST |
| Re: [SI-LIST] : Simulations | Fri Jan 14 2000 - 11:55:36 PST |
| Re: [SI-LIST] : Clamp diodes in models (was Input switching threshold & CPCI) | Mon Jan 10 2000 - 16:24:58 PST |
Sean Murray |
| [SI-LIST] : differential impedance | Thu Apr 20 2000 - 11:18:31 PDT |
Shannon Roseman |
| Re: [SI-LIST] : SI FAQ Proposal | Tue Mar 21 2000 - 21:05:26 PST |
| [SI-LIST] : SpectraQuest vs XTK | Sat Mar 04 2000 - 23:15:28 PST |
Shawn Carpenter |
| RE: [SI-LIST] : Coplanar Transmission Line | Mon Feb 07 2000 - 20:16:55 PST |
Shawn X. Arnold |
| Re: [SI-LIST] : SI Society Chapter | Mon Mar 20 2000 - 18:17:49 PST |
| Re: [SI-LIST] : Where can I get some design informations about CPCI? | Thu Mar 09 2000 - 12:22:15 PST |
| Re: [SI-LIST] : different 4-layer board Stack up (S-P-G-S) ? | Tue Mar 07 2000 - 08:39:09 PST |
| Re: [SI-LIST] : PCB fabrication technology - what's new? | Fri Mar 03 2000 - 08:47:44 PST |
Shayle Hirschman |
| [SI-LIST] : Catching the Corners: chain of synchronizing registers | Sat Mar 18 2000 - 07:31:03 PST |
| Re: [SI-LIST] : Medium range capacitors | Wed Mar 08 2000 - 03:35:44 PST |
| Re: [SI-LIST] : Medium range capacitors | Tue Mar 07 2000 - 12:44:27 PST |
| [SI-LIST] : Medium range capacitors | Tue Mar 07 2000 - 10:20:37 PST |
| RE: [SI-LIST] : Fast edge termination choice | Fri Feb 25 2000 - 08:49:25 PST |
| [SI-LIST] : Fast edge termination choice | Fri Feb 25 2000 - 06:34:27 PST |
[email protected] |
| [SI-LIST] : trace impedance | Tue Mar 14 2000 - 12:50:14 PST |
Silvio ORSI |
| Re: [SI-LIST] : Bulk Caps -> Inductor? -> Plane | Fri Apr 14 2000 - 08:33:06 PDT |
Speer, Ewart |
| [SI-LIST] : interplanar capacitance | Thu Feb 03 2000 - 11:48:46 PST |
Spencer, David H |
| [SI-LIST] : 2 Layer Boards and Ground Grids | Mon Mar 13 2000 - 06:45:31 PST |
SPI Workshop |
| [SI-LIST] : Workshop on Signal Propagation on Interconnects | Wed Jan 26 2000 - 07:51:26 PST |
Steeve Gaudreault |
| [SI-LIST] : Decoupling strategy on 622MHz devices | Thu Apr 06 2000 - 10:19:21 PDT |
Stephanie Goedecke |
| RE: [SI-LIST] : Signal traces without reference plane | Mon Jan 10 2000 - 10:57:22 PST |
Stephen Hilla |
| [SI-LIST] : Signal Integrity Eng. Job Openings at Cisco, RTP, NC | Tue Mar 28 2000 - 10:55:09 PST |
Stephen Nolan |
| Re: [SI-LIST] : Bad IBIS models! | Wed Mar 15 2000 - 14:36:07 PST |
Stephen Peters |
| RE: [SI-LIST] : LVDS questions | Wed Feb 02 2000 - 09:59:56 PST |
| Re: [SI-LIST] : modeling languages (was: receiver jitter) | Thu Jan 20 2000 - 13:05:12 PST |
Steve Ash |
| RE: [SI-LIST] : BLVDS Hot Swap | Tue Apr 11 2000 - 13:29:39 PDT |
| [SI-LIST] : BLVDS Hot Swap | Fri Apr 07 2000 - 14:56:10 PDT |
Steve Corey |
| Re: [SI-LIST] : Question on propagation delay........ | Mon Apr 17 2000 - 11:53:04 PDT |
| Re: [SI-LIST] : Frequency or time domain for component characterization | Mon Feb 28 2000 - 15:19:10 PST |
Steve Ting |
| RE: [SI-LIST] : High Speed Design by Rules of Thumb vs. Simulation | Wed Feb 23 2000 - 00:50:46 PST |
Stuart Adams |
| Re: [SI-LIST] : Number of GND/Power pins in a connector ? | Thu Mar 23 2000 - 14:08:38 PST |
| [SI-LIST] : Number of GND/Power pins in a connector ? | Thu Mar 23 2000 - 07:43:19 PST |
subas |
| [SI-LIST] : SSC | Mon Mar 13 2000 - 23:09:02 PST |
| [SI-LIST] : TDR system information | Tue Mar 07 2000 - 10:41:13 PST |
Sunil Kumar |
| [SI-LIST] : via capacitance | Thu Mar 30 2000 - 21:34:00 PST |
| [SI-LIST] : Ferrite bead | Fri Mar 17 2000 - 00:19:40 PST |
| Re: [SI-LIST] : Looking for ibis reflector subscribing info...... | Fri Feb 11 2000 - 05:59:40 PST |
sweir |
| Re: [SI-LIST] : 18 layer stackup question | Wed Apr 12 2000 - 12:52:20 PDT |
| Re: [SI-LIST] : Bulk Caps -> Inductor? -> Plane | Tue Apr 11 2000 - 17:33:32 PDT |
| Re: [SI-LIST] : PWR/GND grid effect on EMI | Tue Apr 04 2000 - 20:33:02 PDT |
| Re: [SI-LIST] : Daisy-Chain | Wed Mar 22 2000 - 12:46:00 PST |
| Re: [SI-LIST] : Ferrite bead | Fri Mar 17 2000 - 05:05:45 PST |
| Re: [SI-LIST] : SSC | Mon Mar 13 2000 - 23:55:11 PST |
| Re: [SI-LIST] : LVDS driving PCML | Wed Mar 08 2000 - 20:55:23 PST |
| Re: [SI-LIST] : Medium range capacitors | Wed Mar 08 2000 - 10:20:34 PST |
| Re: [SI-LIST] : Medium range capacitors | Tue Mar 07 2000 - 19:21:50 PST |
| Re: [SI-LIST] : Medium range capacitors | Tue Mar 07 2000 - 17:42:00 PST |
| RE: [SI-LIST] : Adding inductors to ground? | Wed Mar 01 2000 - 17:21:52 PST |
| Re: [SI-LIST] : Stack up | Wed Feb 23 2000 - 12:37:05 PST |
| Re: [SI-LIST] : Stack up | Tue Feb 22 2000 - 13:18:39 PST |
| Re: [SI-LIST] : Stack up | Mon Feb 21 2000 - 17:09:13 PST |
| Re: [SI-LIST] : problem with crystal | Fri Feb 18 2000 - 02:08:52 PST |
| Re: [SI-LIST] : interplanar capacitance | Thu Feb 03 2000 - 12:49:25 PST |
| Re: [SI-LIST] : High Speed Backplane Connector Recommendations | Fri Jan 14 2000 - 11:54:22 PST |
| Re: [SI-LIST] : High Speed Backplane Connector Recommendations | Thu Jan 13 2000 - 19:23:23 PST |
| Re: [SI-LIST] : High Speed Backplane Connector Recommendations | Thu Jan 13 2000 - 18:56:08 PST |
Tadashi ARAI |
| Re: [SI-LIST] : Reflections on clock line | Thu Apr 06 2000 - 04:37:39 PDT |
| Re: [SI-LIST] : Bad IBIS models! | Wed Mar 15 2000 - 18:00:48 PST |
| Re: [SI-LIST] : Bad IBIS models! | Thu Mar 16 2000 - 19:47:14 PST |
| Re: [SI-LIST] : SSC | Tue Mar 14 2000 - 00:26:27 PST |
| Re: [SI-LIST] : ribbon cable models | Fri Mar 10 2000 - 01:16:39 PST |
| Re: [SI-LIST] : SpectraQuest vs XTK | Sun Mar 05 2000 - 23:31:57 PST |
| [SI-LIST] : Searching XTK utils. | Wed Feb 23 2000 - 03:03:13 PST |
| Re: [SI-LIST] : XTK vs ICX | Wed Jan 19 2000 - 10:10:28 PST |
Teddy Chou |
| RE: [SI-LIST] : width of the return path | Sun Jan 16 2000 - 19:18:30 PST |
| RE: [SI-LIST] : questions about Spicelink/Ansoft tools | Fri Jan 14 2000 - 01:47:41 PST |
| [SI-LIST] : questions about Spicelink/Ansoft tools | Thu Jan 06 2000 - 19:25:47 PST |
Tham Kok Tong |
| Re: [SI-LIST] : Reflections on clock line | Wed Apr 12 2000 - 17:49:19 PDT |
| [SI-LIST] : Reflections on clock line | Wed Apr 05 2000 - 11:15:04 PDT |
| [SI-LIST] : Daisy-Chain | Mon Mar 20 2000 - 00:26:41 PST |
Tim L. Michalka |
| [SI-LIST] : Position Available | Thu Feb 17 2000 - 15:07:11 PST |
Todd Westerhoff |
| Re: [SI-LIST] : SpectraQuest vs XTK | Mon Mar 06 2000 - 07:47:36 PST |
Tom Dagostino |
| RE: [SI-LIST] : Bulk Caps -> Inductor? -> Plane | Tue Apr 11 2000 - 14:13:36 PDT |
| RE: [SI-LIST] : Return path for stripline, two ground planes or o ne power and one ground? | Mon Apr 10 2000 - 09:17:48 PDT |
| RE: [SI-LIST] : Rambus patent posturing - what gives? | Mon Mar 27 2000 - 03:17:38 PST |
| RE: [SI-LIST] : HSPICE Start Up conditions | Wed Mar 22 2000 - 10:50:21 PST |
| RE: [SI-LIST] : Bad IBIS models! | Fri Mar 17 2000 - 11:51:56 PST |
| RE: [SI-LIST] : Your experience with equivalent circuit modeling tools ... | Fri Mar 10 2000 - 12:02:21 PST |
| RE: [SI-LIST] : LVDS driving PCML | Thu Mar 09 2000 - 08:57:24 PST |
| RE: [SI-LIST] : Zener used to clamp Vcc? | Mon Feb 28 2000 - 14:57:16 PST |
| RE: [SI-LIST] : Zener used to clamp Vcc? | Fri Feb 25 2000 - 16:14:46 PST |
| RE: [SI-LIST] : DSO Selection | Wed Feb 09 2000 - 14:02:54 PST |
| RE: [SI-LIST] : LVDS signal observation | Wed Feb 02 2000 - 10:38:52 PST |
| RE: [SI-LIST] : receiver jitter | Wed Jan 19 2000 - 11:43:05 PST |
| RE: [SI-LIST] : Zo Variance From Plating Thickness Variation | Fri Jan 14 2000 - 15:44:20 PST |
| RE: [SI-LIST] : What's your favourite Screwy SI Concept? | Fri Jan 14 2000 - 09:12:13 PST |
| RE: [SI-LIST] : Clamp diodes in models (was Input switching threshold & CPCI) | Mon Jan 10 2000 - 15:50:53 PST |
| RE: [SI-LIST] : Physcially-small far-end LVDS terminations? | Mon Jan 10 2000 - 11:56:20 PST |
| RE: [SI-LIST] : Clamp diodes in models (was Input switching threshold & CPCI) | Mon Jan 10 2000 - 10:23:11 PST |
Tom Pelc |
| [SI-LIST] : Does anyone have a model for a Meritec PCI connector? | Fri Jan 14 2000 - 11:18:59 PST |
Tom Zimmerman |
| Re: [SI-LIST] : LVDS questions | Wed Feb 02 2000 - 08:57:27 PST |
| [SI-LIST] : LVDS questions | Tue Feb 01 2000 - 12:13:01 PST |
Tony Sweeney |
| Re: [SI-LIST] : AC Coupling vs DC Coupling | Mon Apr 17 2000 - 15:37:33 PDT |
| [SI-LIST] : Spice Consultants? | Tue Mar 28 2000 - 10:52:43 PST |
[email protected] |
| [SI-LIST] : XTK vs ICX | Fri Jan 14 2000 - 05:16:15 PST |
Treytnar Dieter |
| [SI-LIST] : Program: Workshop on SIGNAL PROPAGATION ON INTERCONNECTS | Thu Mar 16 2000 - 01:34:04 PST |
Ulrich Mussler |
| AW: [SI-LIST] : Lab procedures for TDR | Thu Mar 23 2000 - 01:35:33 PST |
| AW: [SI-LIST] : How to measure differential pattern on test coupo n? | Thu Mar 02 2000 - 03:36:20 PST |
Umesh Painaik |
| Re: [SI-LIST] : HSPICE Start Up conditions | Wed Mar 22 2000 - 12:16:32 PST |
Vern Dunbrack |
| [SI-LIST] : Signal Integrity AE for Xilinx | Fri Apr 14 2000 - 12:33:04 PDT |
Vigliarolo Roberto |
| R:[SI-LIST] : Adding inductors to ground? | Mon Mar 06 2000 - 03:26:58 PST |
| R:[SI-LIST] : Zener used to clamp Vcc? | Tue Feb 29 2000 - 01:24:22 PST |
| R:[SI-LIST] : Zener used to clamp Vcc? | Mon Feb 28 2000 - 03:07:21 PST |
| R:[SI-LIST] : LVDS signal observation | Thu Feb 03 2000 - 01:11:49 PST |
Vinu Arumugham |
| Re: [SI-LIST] : Return path for stripline, two ground planes or o ne power and one ground? | Fri Apr 07 2000 - 13:37:59 PDT |
| Re: [SI-LIST] : Reflections on clock line | Thu Apr 06 2000 - 11:50:21 PDT |
| Re: [SI-LIST] : Return path for stripline, two ground planes or one power and one ground? | Tue Apr 04 2000 - 17:10:38 PDT |
| Re: [SI-LIST] : Return path for stripline, two ground planes or o ne power and one ground? | Tue Apr 04 2000 - 12:45:51 PDT |
| Re: [SI-LIST] : Return path for stripline, two ground planes or one power and one ground? | Tue Apr 04 2000 - 12:10:55 PDT |
| Re: [SI-LIST] : Return path for stripline, two ground planes or one power and one ground? | Tue Apr 04 2000 - 11:57:25 PDT |
| Re: [SI-LIST] : Number of GND/Power pins in a connector ? | Thu Mar 23 2000 - 16:27:07 PST |
| Re: [SI-LIST] : Fast edges with limited plane capacitance | Fri Mar 17 2000 - 17:53:21 PST |
| Re: [SI-LIST] : Fast edges with limited plane capacitance | Fri Mar 17 2000 - 11:07:12 PST |
| Re: [SI-LIST] : Fast edges with limited plane capacitance | Fri Mar 17 2000 - 10:50:36 PST |
| Re: [SI-LIST] : trace width for clock routing- wider/narrower? | Mon Mar 13 2000 - 09:47:26 PST |
| Re: [SI-LIST] : Adding inductors to ground? | Thu Mar 02 2000 - 10:35:22 PST |
| Re: [SI-LIST] : Adding inductors to ground? | Wed Mar 01 2000 - 15:35:14 PST |
| Re: [SI-LIST] : Zener used to clamp Vcc? | Fri Feb 25 2000 - 14:56:31 PST |
| Re: [SI-LIST] : montonic signals at SDRAM-, SSRAM- and FEPROM-adress inputs | Fri Feb 11 2000 - 10:12:18 PST |
| Re: [SI-LIST] : Coplanar Transmission Line | Thu Feb 03 2000 - 13:39:52 PST |
| Re: [SI-LIST] : Coplanar Transmission Line | Thu Feb 03 2000 - 12:11:54 PST |
Vipul Badoni |
| [SI-LIST] : HSPICE: Delay and invert a differential signal w.r.t to another. | Thu Mar 02 2000 - 00:02:57 PST |
Volk, Andrew M |
| RE: [SI-LIST] : Printer Port | Mon Apr 10 2000 - 09:15:36 PDT |
| RE: [SI-LIST] : Input switching threshold & CPCI | Tue Jan 04 2000 - 14:34:51 PST |
[email protected] |
| [SI-LIST] : Crossing clock domain boundaries in digital ASICs | Fri Feb 04 2000 - 02:13:01 PST |
Walt Kreiger |
| Re: [SI-LIST] : Coax connection to a CPW guide | Fri Mar 31 2000 - 04:45:09 PST |
Wang Lin |
| [SI-LIST] : EMC techniques on 2-layer board | Thu Feb 03 2000 - 21:33:55 PST |
| [SI-LIST] : environment effects of radiofrequency radiation | Wed Feb 02 2000 - 19:03:49 PST |
WAUGH,RAY (HP-SanJose,ex1) |
| RE: [SI-LIST] : Zener used to clamp Vcc? | Fri Feb 25 2000 - 14:45:42 PST |
| RE: [SI-LIST] : Coplanar Transmission Line | Thu Feb 03 2000 - 15:33:42 PST |
| [SI-LIST] : Clamp diodes in models | Mon Jan 10 2000 - 16:03:45 PST |
| RE: [SI-LIST] : Clamp diodes in models (was Input switchingthresh old & CPCI) | Mon Jan 10 2000 - 15:27:47 PST |
Weber Chuang |
| RE: [SI-LIST] : board-level simulation for differential signals | Thu Apr 13 2000 - 20:04:10 PDT |
| RE: [SI-LIST] : SI Society Chapter | Mon Mar 20 2000 - 18:28:13 PST |
| RE: [SI-LIST] : trace width for clock routing- wider/narrower? | Sun Mar 12 2000 - 18:34:07 PST |
Weston Beal |
| RE: [SI-LIST] : board-level simulation for differential signals | Thu Apr 13 2000 - 09:23:32 PDT |
| [SI-LIST] : meaning and value of C_comp | Tue Mar 21 2000 - 12:19:57 PST |
| RE: [SI-LIST] : SI Software for EMC | Thu Mar 16 2000 - 09:41:06 PST |
| RE: [SI-LIST] : Bad IBIS models! | Wed Mar 15 2000 - 15:18:42 PST |
| RE: [SI-LIST] : Bad IBIS models! | Wed Mar 15 2000 - 15:08:23 PST |
| RE: [SI-LIST] : Your experience with equivalent circuit modeling tools ... | Fri Mar 10 2000 - 09:01:44 PST |
| RE: [SI-LIST] : Opinions on SI CAE tools | Mon Feb 28 2000 - 09:06:01 PST |
| RE: [SI-LIST] : si-list FAQ | Wed Feb 02 2000 - 15:30:07 PST |
| RE: [SI-LIST] : XTK vs ICX | Mon Jan 17 2000 - 08:46:24 PST |
Winson Yu |
| RE: [SI-LIST] : Power noise/ground bounce software | Fri Feb 04 2000 - 17:12:29 PST |
Witte, Markus |
| [SI-LIST] : 3D data interchange | Fri Feb 11 2000 - 07:17:13 PST |
WMA |
| [SI-LIST] : 20-H RULE CONTINUED | Sun Jan 09 2000 - 17:57:55 PST |
[email protected] |
| RE: [SI-LIST] : Signal Integrity Position | Fri Mar 31 2000 - 08:37:36 PST |
Won Chang |
| RE: [SI-LIST] : si-list FAQ | Wed Feb 02 2000 - 14:21:47 PST |
[email protected] |
| [SI-LIST] : SI Software for EMC | Thu Mar 16 2000 - 06:29:34 PST |
X2Y ATTENUATORS, LLC. |
| RE: [SI-LIST] : Rambus patent posturing - what gives? | Mon Mar 27 2000 - 02:58:38 PST |
Yann Noury |
| [SI-LIST] : STTL3 bus terminations | Mon Jan 10 2000 - 11:24:29 PST |
yaserh |
| [SI-LIST] : measuring radiation | Sat Feb 19 2000 - 07:29:12 PST |
| [SI-LIST] : problem with crystal | Thu Feb 17 2000 - 23:21:00 PST |
Yehuda D. Yizraeli |
| [SI-LIST] : HSPICE Control card for simulations with inductors | Sun Apr 02 2000 - 22:21:12 PDT |
| [SI-LIST] : Analog ground connection on PCBoards | Sun Mar 26 2000 - 07:40:05 PST |
| [SI-LIST] : Board simulations, what should it include? | Tue Mar 14 2000 - 09:24:35 PST |
Yu Wang |
| Re: [SI-LIST] : Bulk Caps -> Inductor? -> Plane | Thu Apr 13 2000 - 08:15:58 PDT |
| Re: [SI-LIST] : re: [SI-LiST]: PLL clock buffer chips and the feedback loop | Wed Apr 05 2000 - 21:09:46 PDT |
| Re: [SI-LIST] : Any buffer suggestions? | Sat Mar 25 2000 - 20:08:21 PST |
| Re: [SI-LIST] : how to combine multi components together with Orcad layout | Fri Mar 24 2000 - 07:04:47 PST |
| [SI-LIST] : how to combine multi components together with Orcad layout | Tue Mar 21 2000 - 07:42:43 PST |
| Re: [SI-LIST] : Daisy-Chain | Mon Mar 20 2000 - 07:00:57 PST |
| RE: [SI-LIST] : SSC | Tue Mar 14 2000 - 13:16:05 PST |
Zabinski, Patrick |
| RE: [SI-LIST] :PECL spec? | Wed Jan 26 2000 - 04:44:34 PST |
| RE: [SI-LIST] : **error**: internal timestep too small | Thu Jan 20 2000 - 12:46:45 PST |
Zabinski, Patrick J. |
| RE: [SI-LIST] : on-chip decoupling capacitance (and SI) | Wed Apr 19 2000 - 11:40:18 PDT |
| RE: [SI-LIST] : on-chip decoupling capacitance (and SI) | Wed Apr 19 2000 - 04:46:15 PDT |
| RE: [SI-LIST] : A basic question | Fri Mar 17 2000 - 05:31:50 PST |
| RE: [SI-LIST] : A basic question | Fri Mar 17 2000 - 06:16:01 PST |
| RE: [SI-LIST] : Adding inductors to ground? | Wed Mar 01 2000 - 15:15:02 PST |
| RE: [SI-LIST] : Creating and displaying eye diagrams with Avanti HSpice..... | Thu Feb 17 2000 - 12:45:06 PST |
| RE: [SI-LIST] : High Density Board to Board Connectors? | Mon Feb 14 2000 - 07:40:11 PST |
| RE: [SI-LIST] : Coplanar Transmission Line | Thu Feb 03 2000 - 12:49:20 PST |
| RE: [SI-LIST] : Coplanar Transmission Line | Thu Feb 03 2000 - 11:43:47 PST |
| RE: [SI-LIST] : High-Speed Materials {[DC] & SI-List} | Thu Feb 03 2000 - 10:16:16 PST |
zanella, fabrizio |
| RE: [SI-LIST] : SI Society Chapter | Mon Mar 20 2000 - 11:48:31 PST |
| RE: [SI-LIST] : Your experience with equivalent circuit modeling tools ... | Wed Mar 15 2000 - 10:55:43 PST |
| [SI-LIST] : SI opening at EMC! | Thu Feb 24 2000 - 08:32:08 PST |
| [SI-LIST] : Power noise/ground bounce software | Fri Feb 04 2000 - 12:37:52 PST |
| RE: [SI-LIST] : XTK vs ICX | Fri Jan 21 2000 - 05:29:46 PST |
| RE: [SI-LIST] : **error**: internal timestep too small | Thu Jan 20 2000 - 06:14:01 PST |
| [SI-LIST] : BERT testers | Wed Jan 19 2000 - 04:58:28 PST |
Zhang, Michael T |
| RE: [SI-LIST] : SSC | Tue Mar 14 2000 - 13:35:28 PST |
| RE: [SI-LIST] : SSC | Tue Mar 14 2000 - 09:29:57 PST |
zhoujun |
| [SI-LIST] : Pwr/Gnd Noise | Fri Apr 07 2000 - 09:18:14 PDT |
�L�·� |
| [SI-LIST] : Return path for stripline, two ground planes or one power and one ground? | Thu Mar 30 2000 - 16:59:38 PST |
| RE: [SI-LIST] : trace width for clock routing- wider/narrower? | Mon Mar 13 2000 - 17:00:21 PST |
| [SI-LIST] : trace width for clock routing- wider/narrower? | Sun Mar 12 2000 - 17:04:50 PST |
| RE: [SI-LIST] : Power / Ground simulation | Sun Feb 20 2000 - 18:50:47 PST |
| [SI-LIST] : Power / Ground simulation | Thu Feb 17 2000 - 21:16:26 PST |
| RE: [SI-LIST] : montonic signals at SDRAM-, SSRAM- and FEPROM-ad ress inputs | Fri Feb 11 2000 - 00:21:51 PST |
| RE: [SI-LIST] : XTK vs ICX | Wed Jan 19 2000 - 17:37:03 PST |