RE: [SI-LIST] : tracking/oversampling PLL architectures

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From: Ooi, Thien Ern (thien.ern.ooi@intel.com)
Date: Fri Mar 10 2000 - 17:29:09 PST


Once the appropriate sample has been determined, how frequently does the
sample choice need to be updated? Is a special data pattern needed to
update the sample choice, or random data will do, as long as there is a
certain minimum transistion density?

-----Original Message-----
From: david_instone@uk.xyratex.com [mailto:david_instone@uk.xyratex.com]
Sent: Thursday, March 09, 2000 1:56 AM
To: si-list@silab.eng.sun.com
Subject: Re: [SI-LIST] : tracking/oversampling PLL architectures

<snipped>

In the oversampling PLL, which technically isn't a pll, a local and
relativly stable clock is used to sample the incoming bitstream several
times during each bit period. Logic then determines on a bit by bit
basis which of the several samples is the one to be used. You don't
actually have to have a local clock that is many times the frequency of
the bit rate, just generate several phases of a clock at the bit rate.

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