Re: [SI-LIST] : PLL clock buffer chips and the feedback loop

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From: Rengarajan S Krishnan (a0756869@india.ti.com)
Date: Fri Apr 07 2000 - 09:11:09 PDT


Lynne Green wrote:

> Andy said:
> My prototype board reliably fails to configure itself
>at power-on, but always works after pushing the reset button.
> I saw this on a prototype once. It was caused by random data in
> memory&latches at power-on, while the reset cleared the critical
>latches, leaving the design in a "valid" operational state.
>
> Lynne

Another experience . I have seen this too for slow Power On VDD ramps,
but for a different reason (probably similar to your VME chip!!):

The POR was used to set (latch) a flag - to distinguish between a
 Unlocked condition at POR and an Unlocked condition during
normal operation of the PLL. The (wrong) assumption made was
that the PLL would lock only after the POR (Power ramps up almost
fully up ~ 3.0V). However, the PLL locked at less than 3.0V !! and
the flag was not set!! The logic was such that the chip outputs would
not be active if the flag was off. So, under this situation, the chip
seemed
"dead". A logic reset to the chip could however, rectify this
situation.
It is possible that you have a different situation, Nevertheless just
give it a shot : Try faster VDD ramps (if you can manage that).

Regards
Krishnan

--
R.S.Krishnan, ASIC Product Development Center
Texas Instruments (India) Ltd
GolfView Homes, Murugeshpalaya
Bangalore 560 017 Ph. +91-80-509-9194

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