RE: [SI-LIST] : Parallel Plate Capacitance for Bypass

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From: Knighten, Jim L (JK100005@exchange.SanDiegoCA.NCR.COM)
Date: Fri Mar 24 2000 - 14:44:40 PST


Chris,
 
I think that you will find that this subject area is on the bleeding edge of
our understanding of technology.
 
1. I think you will find that a calculation of parallel plate capacitance
is not very helpful, except to note that some board stackups provide a lower
power bus impedance than others (due primarily to capacitance). Early time
delivery of charge from the power planes is determined more by inductance of
the power plane path than the overall capacitance of the stack.
Considerable research in this area has been done at the University of
Missouri - Rolla. I suggest you contact Prof. Todd Hubing at
thubing@ee.umr.edu <mailto:thubing@ee.umr.edu> for details.
 
2. yes
 
Jim Knighten
NCR
San Diego
848-484-2537

-----Original Message-----
From: Hansen, Chris [mailto:chris_hansen@adaptec.com]
Sent: Friday, March 24, 2000 1:26 PM
To: SI List (E-mail)
Subject: [SI-LIST] : Parallel Plate Capacitance for Bypass

According to specifications, X7R type chip capacitors used for power
subsystem bypass seem to become ineffective above 150 to 200 Mhz. For
frequencies higher up, you are reliant upon the internal parallel plate
capacitance. I have two questions.
 
1. Is the calculation for the required capacitance that is needed for the
parallel plate capacitance the same as that used for a discrete chip
capacitor bypass network, or is there a conservation of charge situation
where the real answer is Cpp*dVnoise = Cload*dVchange? (where Cpp = parallel
plate capacitance, dVnoise = tolerable change in power supply voltage, Cload
= sum of load capacitance being switched simultaneously, dVchange = voltage
change through driver output switch).
 
2. If you have a power plane sandwiched between 2 ground planes, does the
parallel plate capacitance double for a given area?
 
Thank you,
Chris Hansen
Sr. Design Engineer
DPT & Adaptec Companies
 
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