Re: [SI-LIST] : Terminator location with larger BGA's

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From: Scott McMorrow ([email protected])
Date: Sat Apr 08 2000 - 23:42:36 PDT


Bob,

This assumes that the device package inductance is small
enough to be electrically short relative to the rise time
of the signal. As the package inductance increases (i.e. the
package delay increases) the purely capacitive load assumption
of an input is voided. There are a number of cases where 1/4
wave resonators can be created due to package inductance.
In that case, low input capacitance actually worsens the effect.

I've seen some textbook circuits with transmission line impedance
compensation resonate between the pin and die of the package.
These are tough to diagnose without simulation, since the resonance
is burried within the package, and are only evidenced by excessive
jitter in measurements.

regards,

scott

Bob Lewandowski wrote:

> I agree, it's usually better to put a capacitive discontinuity (device input) across the line ahead of the termination than to put it at the end of a stub line beyond the termination. Capacitors at the
> end of a stub get significantly enhanced (multiplied) by the line length of the stub. If you put the capacitive discontinuity on the line ahead of the termination you can make some effort to compensate
> for it by raising the line impedance by narrowing before and after.
>
> ---Bob Lewandowski
>
> Ron Miller wrote:
>
> > A technique which though sub-optimal, helps is to run the traces through the
> >
> > chip pads and continue on to an open area, terminating there. What happens
> > is you get a capacitve glitch on the TDR a few picoseconds before the term.
> >
> > ron miller
> >
> > > -----Original Message-----
> > > From: [email protected]
> > > Sent: Friday, April 07, 2000 1:17 PM
> > > To: [email protected]
> > > Subject: [SI-LIST] : Terminator location with larger BGA's
> > >
> > > We are using some 484 pin BGA's (FPGA's), which have edge rates of about
> > > 170ps.
> > > Using a series termination, it would have to be placed within 1/10 of the
> > > transition length according to Howard Johnson. On FR4, the transition
> > > length
> > > would be .98, making the distance from source to termination .098. It is
> > > not
> > > possible to get all of the required termination's within that distance.
> > >
> > > Aside from slowing down the edges (not desirable), waiting longer for
> > > things to
> > > settle, or going with buried resistance, are there any other solutions for
> > > placement of termination's? How are other people terminating large, high
> > > pin
> > > count devices?
> > >
> > > Thanks
> > >
> > > Bill McGiffin
> > >
> > >
> > >
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--
Scott McMorrow
Principal Engineer
SiQual, Signal Quality Engineering
18735 SW Boones Ferry Road
Tualatin, OR  97062-3090
(503) 885-1231
http://www.siqual.com

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