RE: [SI-LIST] : Clamp diodes in models (was Input switching threshold & CPCI)

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From: Larry Smith (ldsmith@lisboa.eng.sun.com)
Date: Mon Jan 10 2000 - 12:07:43 PST


Brad - the problem with clamp diode models is usually in the parsitics
that are not modeled. When the diode turns on to clamp an IO within
0.7 volts of a rail, where does the current go? It has to go somewhere
on chip. It probably ends up on a power or ground rail.

One problem with this is inductance. There is an inductance associated
with that path. If several IO are active, they may be using the same
path. This may lead to current crowding and L di/dt noise. I suspect
that this is why you are seeing 2-3 volt overshoots. It will be data
dependent and maybe temperature dependent. Low temperature on the
driving chip can speed up the FET's, giving more di/dt and therefor
more overshoot in the parasitic inductance.

Another problem is resistance. The main purpose of protect diodes is
to dissipate ESD energy. The current path of a protect diode might
involve a fairly resistive portion of an NWell or substrate. This
resistance is not very well controlled or modeled. Once again, current
from several IO can end up in the same path and create trouble that you
will never see in the static model for one protect diode.

I remember one situation where we suspected that stray current from
clamp diodes was injecting either holes or electrons into nearby
latches causing them to switch. These are very infrequent, low level
problems that are nearly impossible to diagnose.

IMO, it is best to terminate the net by using controlled impedance
drivers, series resistors or some other form of termination that
absorbs the energy on the net. A clamp diode does not absorb much
energy. It might make the voltage at a receiver 'look' nice, but it
injects current somewhere on the chip. It also leaves a current
waveform on the net that can come back and bite you several time of
flights later.

regards,
Larry Smith
Sun Microsystems

> From: "Bradley S Henson" <bhenson@notes.west.raytheon.com>
> To: si-list@silab.eng.sun.com
> Date: Mon, 10 Jan 2000 11:06:05 -0800
>
> Thanks Tom. I'm sure you're right. We also had a rich history of static clamp
> tests that were fine. The problems I referenced were pattern and in some cases
> temperature sensitive. They produced annoying low failure rate problems hard to
> elicit and track. They are not, nor have they been, common or prevalent. It was
> interesting though to hear the manufacturer tell us in at least one of the cases
> that their diodes were not intended to clamp transmission line transients and
> doing so overstressed their part. This was the "flag" I was eluding to in the
> original response. Back then we simply added a requirement to our procurement
> specs for tolerating short term transients that forward bias the clamps: We
> eliminated the vendor.
>
> We don't see a lot of failures. In fact, in our present designs we have been
> very carefull to eliminate or carefully understand any ringing that would
> forward bias input clamp diodes. On our ASICs, we characterize the clamp
> currents and make sure they are well within the vendors design reliability
> window.
>
> Brad Henson, Raytheon
>
>

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