Re: [SI-LIST] : Fast edges with limited plane capacitance

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From: Dennis Yarak (yarak@apple.com)
Date: Fri Mar 17 2000 - 13:31:22 PST


I have two comments on this discussion:

1) For many of us, the power plane does not exist. My typical design will
have: +5, +6, +3.3, +2.5, +1.8, +5_Sleep, +3_Sleep, +2.5_Sleep, +1.8 Sleep,
you get the picture. For this case I would advocate S-G-S-S-G-S with power
provided in wells on the appropriate signal layer.

2) Those who advocate S-S-G-P-S-S should stack it up ! 0.062 board, minimal
impedance difference for the routing layers, low cost means S 4mil S 20 mil
P 4mil G 20mil S 4 mil S which gives 115 ohms on the outer signal layers and
97 ohms on the inner using 5 mil traces. Alternatively, S 12mil S 12mil P
4mil G 12 mil S 12mil S gives 115 ohms outer and 77 inner. I would find
these hard to work with....and sorry, I need my 5 mil (or even 4 mil)
traces.

S-G-S-S-G-S can give the same impedance on all layers if you wish. Often
best signal quality at the lowest cost with modern CMOS ( no series R ) is
at 40 ohms or less.

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