Re: [SI-LIST] : on-chip decoupling capacitance (and SI)

About this list Date view Thread view Subject view Author view

From: D. C. Sessions (dc.sessions@vlsi.com)
Date: Wed Apr 19 2000 - 13:00:28 PDT


Chris Cheng wrote:
>
> only partially true, in particular with deep submicron device.
> trench isolation on wells tends to have very high resistance
> and very little control on variation. u will be significantly
> off if u base on esr purely on area resistance.
> chris

I was referring to net capacitance. I agree that calculating
the ESR is much uglier.

> -----Original Message-----
> From: D. C. Sessions [mailto:dc.sessions@vlsi.com]
> Sent: Wednesday, April 19, 2000 11:58 AM
> To: si-list@silab.eng.sun.com
> Subject: Re: [SI-LIST] : on-chip decoupling capacitance (and SI)
>
> "Zabinski, Patrick J." wrote:
> >
> > > > > Case in point: we just ran the onchip capacitance extraction
> > > > > for a customer
> > > > > device. 200nm technology, before adding intentional bypass
> > > > > devices, the
> > > > > assorted sources of supply capacitance came to ~230 nF in the
> > > > > 100-1000 MHz
> > > > > range.
> > > >
> > > > D.C.
> > > >
> > > > Can you shed some light as to what you mean by "assorted
> > > > sources of supply capacitance"? It's hard for me to believe
> > > > 230 nF of trace/grid-capacitance, so I'm struggling to figure
> > > > out where it's coming from.
> > >
> > > Most of your logic is quiescent. RAMs especially. And when
> > > you get down to it, that means that you have a great deal
> > > of gate-source capacitance in series with fully-on source-drain
> > > paths. The net effect is a truly enormous amount of charge
> > > reservoir, damped by parallel high-ESR drain-well and
> > > well-substrate capacitance.
> >
> > D.C.,
> >
> > Thanks; this helps.
> >
> > I can understand and reasonably-estimate the effects of the "gate-source
> > capacitance in series with fully-on source-drain paths" without
> > too much difficulty with Spice. However, I have yet to see an effective
> > model within Spice/Hspice that acocunts for the "high-ESR
> > drain-well and well-substrate capacitance"; how do you
> > determine the effective capacitance for these well-capacitances
> > and the associated ESR?
>
> Wet-thumb triangulation from a couple of points. First off, the
> well-substrate junctions are very well understood -- we have excellent
> control over their doping profiles and know to a fine degree what their
> areal capacitance is. Secondly, we can measure it on testers at low
> frequencies. Finally, we don't give a flip what the exact values are
> so long as we can run plausible back-of-the-envelope calculations to
> convince ourselves that there's enough loss in the system to keep the
> Q managable.

-- 
D. C. Sessions
dc.sessions@vlsi.com

**** To unsubscribe from si-list or si-list-digest: send e-mail to majordomo@silab.eng.sun.com. In the BODY of message put: UNSUBSCRIBE si-list or UNSUBSCRIBE si-list-digest, for more help, put HELP. si-list archives are accessible at http://www.qsl.net/wb6tpu ****


About this list Date view Thread view Subject view Author view

This archive was generated by hypermail 2b29 : Thu Apr 20 2000 - 11:36:14 PDT