From: Heiko Dudek ([email protected])
Date: Tue Feb 08 2000 - 07:35:36 PST
Lee,
> Could you label all of the layers in your diagram,
> so we can understand the stackup?
I should have mentioned that it's the top view of the board, not a cross-
section.
TOP VIEW:
___________________________________________________
______________________ |
| | <=PCB
GND Plane | | Boundary
| |
________________________________ |
(<-Receiver) Signal Trace | |
____________________________ | |
| | | |
| | | |
| | | |
| | | |
____________________________| | |
(<-Driver) | |
________________________________| |
| |
_____________________ | |
Second Signal Trace || |
__________________ || |
| || |
| || |
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
CROSS-SECTION:
________________________________
Signal Layer TOP |
________________________________|_________________
Dielectric Material |
__________________________________________________|
Ground Plane GND |
______________________|
Hope this explaines my original question better.
- Heiko
> From [email protected] Tue Jan 11 17:00 MET 2000
> Date: Tue, 11 Jan 2000 07:54:12 -0800
> X-UIDL: 947678874.024
> From: Lee Ritchey <[email protected]>
> MIME-Version: 1.0
> To: [email protected]
> Subject: Re: [SI-LIST] : Signal traces without reference plane
> Content-Transfer-Encoding: 7bit
> X-Received: By mailgate2.Cadence.COM as IAA01921 at Tue Jan 11 08:00:07 2000
>
> Hans,
>
> Could you label all of the layers in your diagram, so we can understand the stackup?
>
> Stephanie Goedecke wrote:
>
> > My experience is that your concerns can be real and depend mostly
> > on the distances and edge rates involved. For your top signal,
> > the "some impedance mismatch" can degrade the signal fatally,
> > depending on the particular set-up. If you have this situation in
> > a real layout, I suggest you do a signal analysis on the board
> > before you have the board built.
> >
> > How relevant is this theory to actual PCB design? I don't know.
> > How relevant is it if your board works?
> >
> > -Stephanie
> >
> > -----Original Message-----
> > From: Heiko Dudek [mailto:[email protected]]
> > Sent: Wednesday, November 17, 1999 8:45 AM
> > To: [email protected]
> > Cc: [email protected]
> > Subject: [SI-LIST] : Signal traces without reference plane
> >
> > Hi,
> >
> > since being involved in a discussion about "routing pcb traces while
> > having
> > partially no ground reference", I would love to get some other opinions.
> > So,
> >
> > assume a setup like this:
> > (Which you can get on systems with multiple GND / VCC potentials
> > easily.)
> >
> > ______________________
> > |
> > GND Plane |
> > |
> > ________________________________
> > (<-Receiver) Signal Trace |
> > ____________________________ |
> > | | |
> > | | |
> > | | |
> > | | |
> > ____________________________| |
> > (<-Driver) |
> > ________________________________|
> > |
> > _____________________ |
> > Second Signal Trace ||
> > __________________ ||
> > | ||
> > | ||
> > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> >
> >
> > Theoretically I would expect some differential mode EMI because of the
> > current loop the return current on the ground plane forms with the
> > signal current.
> > Of course, there's some reflection on the signal trace because of the
> > impedance mismatch; additionally one should see some additional
> > inductance because of
> > the E field stretching (which goes along with H concentrating) serial to
> > the
> > signal trace. Finally, there might be some coupling into the second
> > signal trace.
> >
> > The *BIG* question is, how relevant is this theory (if applicable at
> > all) to
> > actual PCB design ? What are your experiences on this ? How do you
> > control
> > (or better, avoid) this configuration while autorouting ? Do you care at
> > all (if
> > yes, what's the critical edge rate you have to start worrying) ?
> >
> > Thank you very much,
> >
> > Hans Betz
> > Heiko Dudek
> >
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>
>
>
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