From: [email protected]
Date: Tue Mar 14 2000 - 12:50:14 PST
1. my board build from 26 layers and 2.4 mm thickness, the characristic
impedance of trce is aboua 30 ohm, most of traces is kind of point to point
traces with cmos gate loading (10 pf input capacitance), some of traces are long
40 cm and some are short, is any problem with this caracristic impedance to any
kind of trace ? is this impedance is too low ? what is the recommended pcb
characristic impedance ?
2. whole my design is synchronous to central clock, could I stuck horizontal
vertical and again horizontal vertical layers of signals syncronous to same
clock, when the distance between the layers is 3 mil ?
3. is any problem to connect to VME bus 3.3 volt drivers of data adress and
control bus instead of 5 volt drivers ?
4. in the new family of altera there is PLL circiuts, these circuits are analog
and altera recommends to isolte this circuit from the digital power planes, and
to connect to each PLL separate decoupling capacitors of 0.2 uf and bulk
capacitor of 100 uf, could you recommend me how to isolte the planes ? take into
consideration that in my board design I can't place the tantalum capacitors in
the print side, just in the component side, and the devices are fine line bga
with full grid pins and the PLL located in the center of the grid pins.
5. have any one experience with the apex devices ?
6. have any one idea how to increase the characterist impedance of pcb trace of
5 mil width and 3 mil distance from ground ?
Applied Materials ISR
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