From: S. Weir (firstname.lastname@example.org)
Date: Sat Mar 25 2000 - 15:45:55 PST
Quickswitch parts should do nicely, and are available from most logic
manufacturers. They will prevent excess 5V swing from reaching the 3.3V
parts, and allow the 3V swing to get to the backplane. Since these are
NMOS transmission gates, the only delay they contribute is due to parasitic
RC, which can be quite low. Then, the drive strength is whatever else is
on your backplane to/from the DSP. If this is not adequate, then you will
need really fast level shifting buffers. You I know of MICREL single
voltage parts, ( typically used for big DRAM arrays ) that meet your
timing, but I do not know if they have level shifting parts that are that fast.
At 08:12 AM 3/25/2000 +0000, you wrote:
>I need to interface a Motorola DSP chip -- which operates at 3V3 and which
>does not have 5V input tolerance -- to a legacy backplane that uses
>nominally 5V TTL signals.
>For some signals that are read from the backplane, I would like to specify a
>simple (in logic terms) buffer that has this kind of performance:
>* Output levels suitable for driving 3V3 parts if powered from 5V, or
>* 5V input tolerance if powered from 3V3
>* Low delay. preferably Pd lower than 4ns and 3ns would be better.
>* drive suitable for 1 to 4 CMOS loads.
>Since this will be a new logic family design-in I wondered if anyone had
>useful suggestions/experience on which to use?
>Fax 01480 451587
>**** To unsubscribe from si-list or si-list-digest: send e-mail to
>email@example.com. In the BODY of message put: UNSUBSCRIBE
>si-list or UNSUBSCRIBE si-list-digest, for more help, put HELP.
>si-list archives are accessible at http://www.qsl.net/wb6tpu
**** To unsubscribe from si-list or si-list-digest: send e-mail to firstname.lastname@example.org. In the BODY of message put: UNSUBSCRIBE si-list or UNSUBSCRIBE si-list-digest, for more help, put HELP.
si-list archives are accessible at http://www.qsl.net/wb6tpu
This archive was generated by hypermail 2b29 : Thu Apr 20 2000 - 11:35:54 PDT