From: D. C. Sessions ([email protected])
Date: Fri Feb 25 2000 - 14:32:21 PST
Shayle Hirschman wrote:
> SI experts:
> I am interested in making a decision between series source termination and
> parallel termination (probably something like 100 ohms to vcc and 100 ohms
> to gnd) at the destination of a point to point route.
> I want to use the fast slew rate option of the FPGA as the clock is 150 MHz
> and there isn't much timing budget from chip to chip.
> Does series source termination defeat the purpose of selecting the fast
> slew rate option? Will it slow the edge transition time down, or will the
> signal still transition and travel as fast as if there was no termination,
> but simply be divided (thereby depending on the reflection at the
> I suspect the latter, except that I've heard people say that series source
> termination reduces EMI by slowing the edges down. Could it be that it
> reduces EMI, not by slowing the edges down, but rather just simply because
> it terminates? And that, therefore, as far as EMI goes, parallel
> termination would have a similar EMI result?
> If the edge rate does not diminish by using series source termination, then
> I would prefer that method since it uses only one resistor and has no DC
> bias current as does parallel termination.
Series termination reduces the magnitude of the *currents*
involved by nearly half, and reduces the time envelope in
the same way any effective termination does: by reducing
the Q of the network.
If you have short interconnects, you can actually get pretty
reasonable signal quality on a point-to-point net (you were
talking about a point-to-point interconnect, right? The
series term implies that) by putting one resistor in the
middle of the run. It sounds terrible, but manages to
work tolerably well by providing a loss mechanism and by
phase-splitting the reflections.
-- D. C. Sessions [email protected]
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