From: S. Weir (firstname.lastname@example.org)
Date: Fri Mar 24 2000 - 18:41:09 PST
5 mils should yield about 200pF / in sq, before taking away for vias.
At 02:30 PM 3/24/2000 -0800, you wrote:
>Go to the AVX webpage and the American Technical Ceramics web
>pages. They have S-parameters which show that the smaller profile
>ceramics are good to above 1 Ghz.
>Small profile usually means smaller capacitance so you may need
>a small one of .01 uf and a larger one of about .47 uf.
>For frequencys 3 Ghz and up use a capacitive layer in your
>board. Recently I heard that with 5 mil FR4 dielectric you get about
>100pf per square inch. So, using a 2 mil layer would give about 7.5 X
>this value(per square inch).
>>According to specifications, X7R type chip capacitors used for power
>>subsystem bypass seem to become ineffective above 150 to 200 Mhz. For
>>frequencies higher up, you are reliant upon the internal parallel plate
>>capacitance. I have two questions. 1. Is the calculation for the
>>required capacitance that is needed for the parallel plate capacitance
>>the same as that used for a discrete chip capacitor bypass network, or is
>>there a conservation of charge situation where the real answer is
>>Cpp*dVnoise = Cload*dVchange? (where Cpp = parallel plate capacitance,
>>dVnoise = tolerable change in power supply voltage, Cload = sum of load
>>capacitance being switched simultaneously, dVchange = voltage change
>>through driver output switch). 2. If you have a power plane sandwiched
>>between 2 ground planes, does the parallel plate capacitance double for a
>>given area?Thank you,Chris HansenSr. Design EngineerDPT & Adaptec Companies
>Ronald B. Miller _\\|//_ Signal Integrity Engineer
>(408)487-8017 (' 0-0 ') fax(408)487-8017
>Brocade Communications Systems, 1901 Guadalupe Parkway, San Jose, CA 95131
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