From: Zabinski, Patrick ([email protected])
Date: Wed Jan 26 2000 - 04:44:34 PST
I haven't been able to find an official spec anywhere,
but this is what I've learned through experience.
Essentially, PECL is the same as ECL, simply shifted
up in voltage. In ECL, VCC is 0.0V, VTT is -2.0V, and
VEE is -5.2V. In PECL, you need to shift all voltages
by the same amount, with one possible exception.
For example, for +5V PECL, VCC is +5, VTT is +3, and
VEE is 0.0V (Vhi & Vlo shift as well).
The exception comes in with LVPECL where VCC, for example,
is only 3.3V. Then, VTT is +1.3V (not 2V drop from VCC).
However, VEE remains at 0.0V.
A few important notes:
* PECL *is* ECL, simply shifted up in voltage
* the way ECL & PECL output drivers are designed,
VCC must be +2.0V above VTT
* a tranditional ECL component can be used as
PECL component; simply shift all voltages by
+5.0V (check your data sheets to ensure the
part can tolerate a 5.0 vs 5.2 supply).
* when you shift VCC & VTT, Vhi & Vlo shift the
These rules seem to apply for every part I've
worked with. The most authoritative source
I've been able to find to date is a Motorola
App note, AN1406, Rev 1, "Designing with PECL (ECL
at +5.0V)", which says essentialy the same thing.
(you can dowload the app note off the web; sorry,
I don't have the address)
> Does some one have the specifications for PECL I/O?
> I am looking for a standard, such as the one (JEDEC8-9)
> existing for SSTL_2 or other standard I/Os.
> I haven't seen such a spec in the JEDEC website.
> I would appreciate any information.
> Ronnen Lovinger
Pat Zabinski ph: 507-284-5936
Mayo Foundation fx: 507-284-9171
200 First Street SW [email protected]
Rochester, MN 55905 www.mayo.edu/sppdg/sppdg_home_page.html
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