**From:** Istvan NOVAK (*istvan.novak@worldnet.att.net*)

**Date:** Sun Feb 06 2000 - 21:16:05 PST

**Next message:**Gary Steinkogler: "RE: [SI-LIST] : 10 layer board stackup Revisited"**Previous message:**Istvan NOVAK: "[SI-LIST] : DesignCon20000 paper posted"**In reply to:**Douglas C. Smith: "Re: [SI-LIST] : ESR and bypass caps"**Next in thread:**Scott McMorrow: "Re: [SI-LIST] : ESR and bypass caps"**Reply:**Scott McMorrow: "Re: [SI-LIST] : ESR and bypass caps"

DougS,

As Ray pointed out, Larry's deck was for the single-node analysis. To

illustrate the effect of capacitor locations, I compiled a short slide show

from various simulation results, it is posted in

http://home.att.net/~istvan.novak/ under illustration tools. On each page

there are self-impedance profiles of a 8"x8" plane pair with 2-mil FR4

dielectrics, with four different conditions: 1) bare planes, 2) 0.1uF bypass

capacitors all in the center, 3) the same number of 0.1uF bypass caps spread

evenly around the board periphery, and 4) the same number of resistive

termination evenly spread along the board periphery. From the many

simulated scenarios probably these four represent the most interesting

extreme corners. The impedance on a one-inch grid was simulated between the

planes and the impedance magnitudes are plotted in ohms. The successive

pages correspond to different frequencies. Note that here no attempt was

made to smooth out the impedance profile by selecting a range of capacitance

values, instead the emphesis was on the variation with capacitor location.

Istvan Novak

SUN Microsystems

----- Original Message -----

From: Douglas C. Smith <doug@dsmith.org>

To: <si-list@silab.eng.sun.com>

Sent: Saturday, February 05, 2000 9:15 AM

Subject: Re: [SI-LIST] : ESR and bypass caps

*> Hi All,
*

*>
*

*> I think the simulation below is missing some key ingredients, the
*

*> variable
*

*> time delay between the capacitors representing their spacing on the
*

*> board
*

*> and loading of the devices. I see below caps connected between vdd and
*

*> 0.
*

*> I have observed that devices lower the Q of the whole structure.
*

*>
*

*> The ground and power planes look to me like a 2 dimensional
*

*> transmission
*

*> line with random hi-Z and lo-Z connections. A simple simulation of
*

*> caps
*

*> in parallel may not give a useful answer unless the caps are right
*

*> next
*

*> to each other. I would like to see the spice model of the 2
*

*> dimensional
*

*> transmission line modeled to a few GHz. (lots of elements!!)
*

*>
*

*> DougS
*

*>
*

*> Doug Brooks wrote:
*

*> >
*

*> > >
*

*> > >Then we have to space capacitors close together in value. This
*

*> > >prevents the parallel resonance from getting too high. The attached
*

*> > >spice deck and .pdf file shows two combinations of capacitors. The
*

*> > >first set has 5 closely spaced values and the second set has just two
*

*> > >values. Inductance is 1nH and ESR is 100mOhms:
*

*> > >
*

*> > >xcap2 vdd 0 cap C=1.0n R=100m L=1n $npo
*

*> > >xcap3 vdd 0 cap C=1.5n R=100m L=1n $npo
*

*> > >xcap4 vdd 0 cap C=2.2n R=100m L=1n $npo
*

*> > >xcap5 vdd 0 cap C=3.3n R=100m L=1n $npo
*

*> > >xcap6 vdd 0 cap C=4.7n R=100m L=1n $npo
*

*> > >
*

*> > >...and...
*

*> > >
*

*> > >xcap2 vdd 0 cap C=1.0n R=100m L=1n $npo
*

*> > >xcap3 vdd 0 cap C=1.0n R=100m L=1n $npo
*

*> > >xcap4 vdd 0 cap C=1.0n R=100m L=1n $npo
*

*> > >xcap5 vdd 0 cap C=4.7n R=100m L=1n $npo
*

*> > >xcap6 vdd 0 cap C=4.7n R=100m L=1n $npo
*

*> > >
*

*> > > >From the spice output you can readily see the parallel resonance and
*

*> > >how dangerous it is when capacitors are not spaced closely in value.
*

*> > >(One ac amp has been forced into the parallel circuit, so volts is
*

*> > >interpreted as magnitude of impedance.) With the 5 different valued
*

*> > >capacitors, we see 4 parallel 'antiresonances', growing with increasing
*

*> > >frequency. The growth is because Q increases as omega increases. The
*

*> > >higher the resonant frequency, the more important it is to have low
*

*> > >inductance pads. The 5 capacitor-value case has a maximum impedance of
*

*> > >about 150 mOhm, but the 2 capacitor-value case has a maximum of about
*

*> > >600 mOhms. That is enough difference to make a product pass or fail.
*

*> > >
*

*> > >With 5 capacitors, we have made a nice flat 100 mOhm impedance
*

*> > >between 60MHz and 200Mhz. With 50 capacitors, we could have made a
*

*> > >10 mOhm impedance between those frequencies. If only we could get a
*

*> > >bunch of 100 mOhm capacitors...
*

*> > >
*

*> > >Members of the SI community should feel free to take this generic
*

*> > >spice deck and run it. Play around with ESR and inductance. You
*

*> > >will quickly see the value of using low ESR capacitors on low
*

*> > >inductance pads in managing a low impedance power system across
*

*> > >a broad frequency range. I believe the same results will be obtained
*

*> > >with Doug Brooks' simulator. Doug, please let us know.
*

*> >
*

*> > My pleasure. Here is what our little calculator would come up with:
*

(Just

*> > like you said.)
*

*> >
*

*> > Case 1:
*

*> >
*

*> > 2/4/2000
*

*> > 4:26:12 PM
*

*> > Initial Conditions
*

*> > Input filename = C:\POLEZERO\LSMITH1.TXT
*

*> > Output filename = C:\POLEZERO\LSMITHO1.TXT
*

*> > Number of Capacitance Values = 5
*

*> > Total Capacitance = .0127
*

*> >
*

*> > Number L nH C
*

*> > uF R Resonant F (MHz)
*

*> > 1 01.00000 .001000
*

.1

*> > 159.155
*

*> > 1 01.00000 .001500
*

.1

*> > 129.949
*

*> > 1 01.00000 .002200
*

.1

*> > 107.302
*

*> > 1 01.00000 .003300
*

.1

*> > 87.612
*

*> > 1 01.00000 .004700
*

.1

*> > 73.413
*

*> >
*

*> > Frequency (MHz) Impedance Turn PhaseAngle(Deg)
*

*> > 72.023 .0675823 Min -36.5026
*

*> > 79.716 .0789909 Max -20.0925
*

*> > 86.671 .0699806 Min -7.6151
*

*> > 97.674 .1031926 Max 2.0211
*

*> > 107.66 .0733426 Min 10.7
*

*> > 119.99 .1153441 Max 18.4003
*

*> > 131.31 .0726022 Min 26.9647
*

*> > 148.33 .1355461 Max 34.9443
*

*> > 161.9 .0699509 Min 43.9007
*

*> > 4:27:00 PM
*

*> >
*

*> > Case 2:
*

*> >
*

*> > 2/4/2000
*

*> > 4:28:38 PM
*

*> > Initial Conditions
*

*> > Input filename = C:\POLEZERO\LSMITH2.TXT
*

*> > Output filename = C:\POLEZERO\LSMITHO2.TXT
*

*> > Number of Capacitance Values = 2
*

*> > Total Capacitance = .0124
*

*> >
*

*> > Number L nH C
*

*> > uF R Resonant F (MHz)
*

*> > 3 01.00000 .001000
*

.1

*> > 159.155
*

*> > 2 01.00000 .004700
*

.1

*> > 73.413
*

*> >
*

*> > Frequency (MHz) Impedance Turn PhaseAngle(Deg)
*

*> > 72.771 .0493910 Min -9.489
*

*> > 115.13 .5864965 Max -1.0232
*

*> > 159.78 .0327716 Min 9.0943
*

*> > 4:29:07 PM
*

*> >
*

*> > .
*

*> > ************************************************************
*

*> > See our updated message re in-house seminars on our web page
*

*> > .
*

*> > Doug Brooks, President doug@eskimo.com
*

*> > UltraCAD Design, Inc. http://www.ultracad.com
*

*> >
*

*> > **** To unsubscribe from si-list: send e-mail to
*

majordomo@silab.eng.sun.com. In the BODY of message put: UNSUBSCRIBE

si-list, for more help, put HELP.

*> > si-list archives are accessible at http://www.qsl.net/wb6tpu
*

*> > ****
*

*>
*

*> --
*

*> -----------------------------------------------------------
*

*> ___ _ Doug Smith
*

*> \ / ) P.O. Box 1457
*

*> ========= Los Gatos, CA 95031-1457
*

*> _ / \ / \ _ TEL/FAX: 408-356-4186/358-3799
*

*> / /\ \ ] / /\ \ Mobile: 408-858-4528
*

*> | q-----( ) | o | Email: doug@dsmith.org
*

*> \ _ / ] \ _ / Website: http://www.dsmith.org
*

*> -----------------------------------------------------------
*

*>
*

*> **** To unsubscribe from si-list: send e-mail to
*

majordomo@silab.eng.sun.com. In the BODY of message put: UNSUBSCRIBE

si-list, for more help, put HELP.

*> si-list archives are accessible at http://www.qsl.net/wb6tpu
*

*> ****
*

*>
*

**** To unsubscribe from si-list: send e-mail to majordomo@silab.eng.sun.com. In the BODY of message put: UNSUBSCRIBE si-list, for more help, put HELP.

si-list archives are accessible at http://www.qsl.net/wb6tpu

****

**Next message:**Gary Steinkogler: "RE: [SI-LIST] : 10 layer board stackup Revisited"**Previous message:**Istvan NOVAK: "[SI-LIST] : DesignCon20000 paper posted"**In reply to:**Douglas C. Smith: "Re: [SI-LIST] : ESR and bypass caps"**Next in thread:**Scott McMorrow: "Re: [SI-LIST] : ESR and bypass caps"**Reply:**Scott McMorrow: "Re: [SI-LIST] : ESR and bypass caps"

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