From: D. C. Sessions (email@example.com)
Date: Fri Mar 03 2000 - 08:07:11 PST
Keith Amundsen wrote:
> We have been looking at creative power plane connections. For subsystems on
> a board (of one or more chips) we are considering isolating the power plane
> under each of them. This would be done with a narrow moat between the
> rectangular island and the rest of the power plane. The moat would be
> bridged with ferrites. The island would have a bulk storage (10 or 33uF)
> for each ferrite and a number of bypass (multiple values) capacitors for
> each chip. These would be connected to the solid ground plane. Their are
> many pros and cons to doing this and we thought a wider audience might help.
This is standard Philips practice for low-EMI products. Works like a champ
UNLESS you have fast edge rates, except that we use a double ground plane
to prevent plane-crossing noise and route power on signal layers. When we
use it we are dealing with I/O cells with explicit edge-rate control on the
order of 10 ns -- which may be an issue for you if you don't have access to
edge-rate limited drivers or have timing budgets that won't stand the delay.
If you use this, make sure you use lossy ferrites or resonance will getcha.
-- D. C. Sessions firstname.lastname@example.org
**** To unsubscribe from si-list or si-list-digest: send e-mail to email@example.com. In the BODY of message put: UNSUBSCRIBE si-list or UNSUBSCRIBE si-list-digest, for more help, put HELP. si-list archives are accessible at http://www.qsl.net/wb6tpu ****
This archive was generated by hypermail 2b29 : Thu Apr 20 2000 - 11:35:17 PDT