Re: [SI-LIST] : Input switching threshold & CPCI

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From: D. C. Sessions (dc.sessions@vlsi.com)
Date: Tue Jan 04 2000 - 15:08:58 PST


"Volk, Andrew M" wrote:
>
> I have to disagree with the comment from Mr. Sessions that compatibility
> from PCI to AGP was not required. It most certainly was. Several vendors
> "bridged" between PCI and AGP with the same controller working on both
> interfaces. They were able to use their prior designs and get into a new
> market quicker, with less risk and lower cost. I'm not saying that the SI
> issue he raised is not correct. There are always better solutions if you
> can cut and run. I'd like to see his "clean sheet" idea actually create a
> better means for interconnect. But "compatibility" is a bridge to better
> things as well as an anchor to them. (I swear by it and at it every day.)

AGP is a point-to-point network, and no PCI devices need apply
*in*a*particular*instance*. Intel should have learned from their disastrous
attempt to allow 5v versions of PCI (remember? it was supposed to be a 3.3v
bus with 5v only allowed briefly to get it started. Instead, it will go into
oblivion as the only 5v part of a low-voltage system.)

AGP was already electrically incompatible (2/3 drive strength, although that
was a late addition -- the AGP spec distributed prior to the review meeting
in Hillsboro that August called for full PCI drive but both Intel and VLSI
engineers flagged that as a mistake and it was fixed before the meeting.)
Since the input thresholds were set by comparators it would have been MUCH
easier to set them at 0.5 Vcc, and the outputs were reduced so making them
symmetrical would also have been no problem.

Yes, this is 20-20 hindsight. But I was there and all of this was pointed
out to Intel before the first AGP devices ever saw silicon.

> -----Original Message-----
> From: Adrian Shiner [mailto:adrian.shiner@virgin.net]
> Sent: Tuesday, January 04, 2000 11:23 AM
> To: si-list@silab.eng.sun.com
> Subject: Re: [SI-LIST] : Input switching threshold & CPCI
>
> Size does not necessarily mean that you have the best thoughts..dinosaurs
> were pretty big but where are they now?
>
> Adrian
> ----- Original Message -----
> From: D. C. Sessions <dc.sessions@vlsi.com>
> To: <si-list@silab.eng.sun.com>
> Sent: 04 January 2000 17:44
> Subject: Re: [SI-LIST] : Input switching threshold & CPCI
>
> > Abe Riazi wrote:
> > >
> > > D. C. Sessions Wrote:
> > > >
> > > >PCI does the old (idiotic) 0.8-2.0 input thresholds that were first
> > > >documented on cave walls. In contrast, anyone trying to do serious
> > > >signaling at nontrivial speeds uses very tight thresholds, usually
> > > >scaled to the driver supply and usually with differential receivers.
> > > >
> > > Hi D. C.,
> > >
> > > This is a good point. For 3.3 V signaling, the input voltage threshold
> > > values (based on PCI specs) consist of:
> > >
> > > Minimum Vih (Input High Voltage) = 0.5 Vcc
> > > Maximum Vil (Input Low Voltage) = 0.3 Vcc
> >
> > Hmmm... 0.9v to 1.8v -- slightly tightened TTL again.
> > The big evil of course is the 0.4 Vcc centerpoint, which
> > Intel reflects in their drive specs making for rotten
> > line matching. They made the same mistake with AGP
> > (Vref of 0.39 to 0.41 Vcc, 2/3 PCI drive) even though
> > there wasn't any need for backward compatibility.
> >
> > At least it's scaled. I'm tired of arguing with customers
> > who insist on running timing analyses against Vih(max) at
> > slow corner Vcc min.
> >
> > --
> > D. C. Sessions
> > dc.sessions@vlsi.com
> >
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-- 
D. C. Sessions
dc.sessions@vlsi.com

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