Re: [SI-LIST] : AC Coupling vs DC Coupling

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From: Josip Popovic (popovic@mosaid.com)
Date: Tue Apr 18 2000 - 04:57:50 PDT


sween@lsil.com wrote:
> Supply noise has the effect of modulating the buffer delay. So it would
> be helpful
> to model a group of 5 output buffers as follows.

Here I would like to add that there are two effect to be considered:

#1. for example a few drivers, that share one gnd pin, and transition
from '1' to '0' would create a voltage drop over the gnd pin. This would
in return slow down discharge of load capacitance(s) (receiver input
capacitance, for example 8 pF). More drivers, larger the voltage drop
over the gnd pin, smaller load discharge currents, slower output
transitions

#2. The same gnd voltage drop would tend to decrease conductivity of the
N channel output transistors, however most of output stages have a pre
driver section that is referenced to the same gnd. This in return would
give that voltage of the gate of the N channel transistor to the
transistor source is differentially always the same. Consequently #2 is
not of such importance as #1.

Josip Popovic

sween@lsil.com wrote:
>
> I agree with Scott McMorrow's response and would like to add:
>
> Things like packages and connectors can be significant contributers to
> ISI. Another big contributer is SSO noise on the power supply lines and
> to
> a lesser extent crosstalk in the bondwires, package and board.
> Supply noise has the effect of modulating the buffer delay. So it would
> be helpful
> to model a group of 5 output buffers as follows.
>
> - model the chip to chip interconnect
> - buffer, bondwire, package, via, transmission line (lossy & coupled),
> via, package, bondwire, input buffer
> - you may have connectors and therefore multiple transmission lines also
> - model the power supply through the package
> - do not assume a perfect supply on the board
> - get bondwire, and package models that have coupling built in.
>
> - put a psuedo random bit pattern on the middle line
> - put a 1010 pattern on the other four lines
>
> - a big spice model like above and a 128 bit pattern would take ~10
> hours to run
> a single case (on a Sun server) so you might want to create a psuedo
> psuedo bit pattern.
>
> Simulation is a good tool but real boards are the only way to really
> know.
> HSPICE and XTK can be great tools to debug some obvious problems up
> front
> and you can see some things you cannot measure on the scope (true cycle
> by
> cyle setup and holds, true cyle to cyle jitter magnitudes).
>
> Regards,
>
> Tony
>
> Scott McMorrow wrote:
> >
> > "Greim, Michael" wrote:
> >
> > > What is an effective method of quantifying
> > > ISI's effect on jitter. Within a simulation, would
> > > the narrowing of an eye pattern indicate this.
> >
> > Yes, a good comparison would be to simulate
> > a pseudo random pattern and then compare it
> > to a simple pattern with a large number of ones
> > followed by a large number of zeros.
> >
> > >
> > > Would the difference between a pseudo random
> > > bit sequence and a clock creating the eye show
> > > this for a given topology?
> >
> > Yes, this third comparison is also quite useful
> >
> > regards,
> >
> > scott
> >
> > > Thanks for the help.
> > >
> > > MG
> > >
> > > > So ... whether on not non-DC balanced data will work in a system is
> > > > dependent upon the available jitter and skew margin at the receivers
> > > > and other sources of noise, jitter and skew in the system. ISI can
> > > > be simulated to determine the upper bounds on it's contribution to
> > > > jitter.
> > > >
> > >
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> >
> > --
> > Scott McMorrow
> > Principal Engineer
> > SiQual, Signal Quality Engineering
> > 18735 SW Boones Ferry Road
> > Tualatin, OR 97062-3090
> > (503) 885-1231
> > http://www.siqual.com
> >
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>
> --
> Anthony C. Sweeney
>
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