RE: [SI-LIST] : Adding inductors to ground?

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From: S. Weir (weirsp@a.crl.com)
Date: Sat Mar 04 2000 - 04:16:06 PST


Mike,

The isolation is for the VCO, not the driver section. If you disturb the
VCO in a PLL with some noise source, then the loop output timing drifts
until the loop recovers. The loop bandwidth on many embedded PLL's is
quite low, and there are also many that have high divide ratios, ( also low
loop b/w ). It doesn't take much noise at all to result in a great deal of
accumulated interval error.

I've also seen similar comments, and think they come from a poor
understanding of physics. It's all that can be done to keep the rails of
high powered devices from collapsing, intentionally inserting impedance in
series with the supply seems a recipe for disaster. As to the clock
drivers, well, in modern processors about half the chip power is the
internal clock drivers.

Regards,

Steve.
At 07:48 AM 3/3/2000 -0600, you wrote:
>Someone tried to tell me that connecting the VCC pins of clock drivers to
>the plane through inductors would "keep noise off of the planes". But the
>whole point of a properly designed power distribution system is provide a
>low impedance over a large frequency range. If your power distribution
>system has a high impedance at a frequency that your clock buffer is drawing
>current, then the problem is the power distribution system and not the clock
>driver's connection to it. And do clock drivers draw more high frequency
>current than modern processors? I doubt it.
>
>============================================================================
>=
>Mike Mayer Artesyn Communication Products, Inc
>Senior Hardware Design Engineer Madison, WI
>Mike.Mayer@cp.artesyn.com http://www.artesyn.com/cp
>============================================================================
>=
>
>
> > -----Original Message-----
> > From: Ritchey Lee [mailto:leeritchey@earthlink.net]
> > Sent: Thursday, March 02, 2000 7:47 PM
> > To: si-list@silab.eng.sun.com
> > Subject: Re: [SI-LIST] : Adding inductors to ground?
> >
> >
> > It's a common practice that is a bad idea. Can't say how it
> > got started, but it's a sure way to degrade the performance of parts.
> >
> > Lee
> >
> > Chris Bobek wrote:
> >
> > > Hi,
> > >
> > > I came across a schematic that shows the PLL ground of an
> > IC connected
> > > to ground through an inductor. The Vcc pin of the device
> > is connected
> > > to a bunch of caps and an inductor to Vcc.
> > >
> > > I understand and have used an inductor (or a resistor) with
> > a bunch of
> > > decoupling caps on Vcc for applications like this. But, I've always
> > > tied the Gnd pin(s) directly to ground. It doesn't make
> > any sense to me
> > > why you would want to add inductance in the path of any ground. It
> > > seems you would just add switching noise to your device.
> > >
> > > Can somebody explain whether this is common practice, or
> > whether it was
> > > a poor design (sorry I don't have more information on the particular
> > > device).
> > >
> > > Thanks,
> > >
> > > Chris
> > >
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