RE: [SI-LIST] : **error**: internal timestep too small

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From: Mellitz, Richard (richard.mellitz@intel.com)
Date: Thu Jan 20 2000 - 13:38:05 PST


We've done "the hook the nodes to ground (or power) trick" too with medium
value resistors. When this fails or it affects resonance more than we'd
like, we got a circuit that shorts the floating power/ground nodes to
power/ground for time and then lets it go.

Try this:

Vtest vtest 0 DC=1.5
Ltest1 Vtest rtest1 3n
Rtest1 rtest1 Vdeliver1 40m
Ctest1 Vdeliver1 0 350p
.tran 10p 12n

This produces a very nice 3 volt sine wave. Image you are modeling this as
your power delivery network. Ought-oh!!!

There some ways we've got to improve this situation. One has already been
mentioned by Arpad. That is use IC.

Vtest vtest 0 DC=1.5
Ltest2 Vtest rtest2 3n ic=0
Rtest2 rtest2 Vdeliver2 40m
Ctest2 Vdeliver2 0 350p ic=1.5
.tran 10p 12n

This still produces a 20 mv spike at time t=0+. This us usually not a
problem. Once in a while, when the circuit get complex, this spike can grow
large enough to give you ITTS.

This spike can be further reduced by.

Vtest vtest 0 DC=1.5
Ltest3 Vtest rtest3 3n ic=0
Rtest3 rtest3 Vdeliver3 40m
Ctest3 Vdeliver3 0 350p
* short the delivery node for some number of ps.
Xstab3 Vdeliver3 Vtest_INIT
.tran 10p 12n

Where Vtest_INIT is the secret sauce :-)

Rich Mellitz,
Intel

-----Original Message-----
From: Zabinski, Patrick [mailto:zabinski.patrick@mayo.edu]
Sent: Thursday, January 20, 2000 3:47 PM
To: 'si-list@silab.eng.sun.com'
Subject: RE: [SI-LIST] : **error**: internal timestep too small

> 1) Increase RELV, and/or RELI if it doesn't hurt your accuracy needs.
> 2) Use .IC to initialize nodes. Nodes that are (almost) floating
> can solve to about anything and setting them to something helps
> a great deal.
> 3) I observed this with the U-element in HSPICE (anyone still using
> it?). If you connect more than two of them to the same node it
> will blow up (with kVolt differences on the two ends of the same
> element). However, a small resistor (yes, resistor) between the
> U-elements and the common joint will allow it to converge. Anyone
> knows why?
>

I cannot claim to know why this works, but if RELV, RELI, IC,
or NODESET helps convergence or if there are problems
with any form of transmission line (T, U, or W), I
simply insert 500K ohm resistors from various nodes to
node 0 (ground). Generally, the value is high enough
to not effect the results, but I've found it not only helps SPICE
find its way, but it can shave off 50-80% off run-time
as well (depending upon the circuit).

For example, I have an SSN simulation setup right now where
I have three layers of W-elements between the driver
and the board (bond wires, package, connectors). When
I originally set up the circuit, SPICE would not converge.
I then inserted these resistors at various points, and
the runs completed successfully. I then added two more
resistors, and the runs produced the sames results in
half the time.

I don't have any easy to describe rules for where
to insert these resistors, but I've picked up a pretty
good 'feeling' for it over the years. Next time
you run into the same problem, I suggest giving it
a shot.

Good luck,
Pat

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