From: Greim, Michael (firstname.lastname@example.org)
Date: Tue Mar 07 2000 - 05:28:51 PST
I don't find this stack-up all that unusual. It is always
better to route over a contiguous plane to minimize
impedance bumps and minimize return currents. Addi-
tionally your designer is right in the fact that you should
have more routing resources on the back side as you
should only have to deal with vias and potentially test
points. If you have a symetric stackup (and you should)
then the impedances should be the same. More
routing resources equate to shorter runs and that coupled
with a contiguous reference plane should offer you the
best possibility of clean signals. Now if you make sure
that you have a properly designed power distribution system
(low impedance across the relavent frequency range) you
are in business.
> -----Original Message-----
> From: Alex Li [SMTP:email@example.com]
> Sent: Monday, March 06, 2000 9:36 PM
> To: 'firstname.lastname@example.org'
> Subject: [SI-LIST] : different 4-layer board Stack up (S-P-G-S) ?
> Recently I saw a 4-layer mother board with 100 Mhz 128-bit memory bus.
> This board has unusual signal-power-ground-signal stack up. I talked to
> one of their engineer for this kind of arrangement. They said since most
> PC motherboard has several power plane split and on the top level there
> are a lot of components with pads. they think if they route all the
> 128-bit memory bus on the back and put it close to ground plane, they have
> much routing area and this will help to keep the signals clean.
> This is kind of new idea to me, does anyone see any drawback by this
> arrangement ? Will this decrease the decoupling caps performance ?
**** To unsubscribe from si-list or si-list-digest: send e-mail to email@example.com. In the BODY of message put: UNSUBSCRIBE si-list or UNSUBSCRIBE si-list-digest, for more help, put HELP.
si-list archives are accessible at http://www.qsl.net/wb6tpu
This archive was generated by hypermail 2b29 : Thu Apr 20 2000 - 11:35:19 PDT