Re: [SI-LIST] : 20-H Rule and Self-Resonant Frequency of Power Planes

About this list Date view Thread view Subject view Author view

From: Scott McMorrow ([email protected])
Date: Thu Apr 13 2000 - 10:48:15 PDT


I figured I would go to the horse's mouth and ask Mark Montrose to comment
about this statement himself. Here is his response:


As requested, here is the answer to your question. I apologize for the delayed
response due to recent travel without Internet access. Please posted to si-list for
me. Technical information regarding 20-H, why and how it works, will be made
available for world-wide release in 4-6 weeks with a 2nd edition of the book
referenced. This new edition will help explain my brief comments below in much
greater detail.

>A number of us on the SI reflector are confused by the following quote from
>your book:
>Page 54 of Mark I. Montrose's book "Printed Circuit Board Design Techniques
>EMC Compliance" (IEEE Press, 1996) has the following statement:
>"Many multilayer PCBs generally have a self-resonant frequency between 200
>400MHz. Use of the 20-H rule (see section 2.2) may increase the self-resonant
>frequency by a factor of 2 to 3."
>Would you be able to explain your rational for an increase in
>the self-resonant frequency by a factor of 2 or 3 by using the 20H rule? This
>does not seem to follow from the Physics of parallel plate waveguides where
>the self-resonant frequency is largely dictated by the velocity of propagation
>of the dielectric and the physical dimensions of the board. The 20H rule
>would hardly alter the physical dimensions to such an extent as to cause a 2 or
>3 increase as you state.

My book that you refer to, has a target audience of PCB designers, and
"non-EMC" engineers (refer to Pages 1 and 2), and was NOT written for
engineers or for those involved in advanced aspects of system design and signal
integrity analysis (i.e., users of this reflector). This is a problem one encounters
when writing a book - the target audience. Those on si-list would benefit more from
my second book, "EMC and the PCB - Design, Theory and Layout Made Simple."
This book targets experienced engineers, and contains solid EMC theory and
analysis. This new book is not appropriate for the audience of PCB Design
Techniques for EMC Compliance. Because of the target audience, in which the
Introduction "clearly" identifies, I did not provide sophisticated details on a complex
topic such as 20-H. With this email, I will now provide brief details on why this
design technique works.

The "self-resonance situation," noted in the statement within my book, refers to
reflection and flux-phase-skews that reactive terminations present at the end of a
transmission line, if proper termination is not provided. Power and ground planes
are in reality transmission lines, and must be treated as such.

Using a typical inductive model of approximately 3 nanoHenries/square centimeter
that both ground/power planes can exhibit (because the chemical etching for
laminate bonding can exceed one skin depth in copper), the "surface area" of the
board may be extensively larger than it would appear from mechanical
dimensions. This is in conjunction with a second order effect of interplane
capacitance between the power and ground planes. Interplane capacitance can
exhibit as much as a 10:1 variance, depending on the dielectric constant, physical
size of the planes, and distance separation. The self-resonant frequency (SRF) of
a capacitor is based on both inductive and capacitive characteristics inherent
within its structure. One tends to forget that the power and ground planes must be
considered separate from discrete capacitors for this analysis. Discrete
capacitors scattered throughout the assembly allows for a distributed effect to be
observed with both poles and zeros when combined with the power and ground
plane assembly. The use of discrete decoupling capacitors has no effect on how
and why the 20-H rule works, which is where past discussion on self-resonance
regarding this issue has occurred on the reflector, and why that analysis is totally

Assume that a larger size PCB with a large edge area, (greater than several
square inches around the perimeter) is NOT terminated by components or utilized
by devices and loads. The reflection time constant from the reflected
electromagnetic wave from all edges of the board, reflected simultaneously back
to the source driver, may indeed bring the overall parallel-plane SRF down to the
frequency range of 200 to 400 MHz. Because not all PCBs are square, the
reflected wave hits the edge boundary of the PCB, observes an edge boundary
discontinuity, and reflects back into the PCB structure. Depending on whether the
wave front is coming or going, EMI may occur if termination is not provided for the
transmission line, with some energy radiating off the edge of the board into free
space or energizing a cavity structure. Multiply this effect with hundreds of device
pins switching asynchronous, each with a reflected wave that propagates radially
from the source driver, each with a reflection. This is the primary reason why it is
difficult, if not nearly impossible to simulate 20-H for a fully populated assembly.
This is an EMI (electromagnetic field ) issue requiring frequency domain analysis,
and cannot be solve using SPICE or derivations of this simulation tool. One must
examine 20-H with "many" component active, not just one stimulation source. This
is a primary reason why simulation of 20-H in the time domain is not easily

The purpose for undercut of the voltage plane by a physical dimension (i.e., 20-H),
is to remove an un-terminated stub caused primarily by unterminated planes. For
this scenario, substitute the words "transmission line" for planes. When doing so,
the concept becomes easier to visualize. When this perimeter "stub" is sufficiently
large, based on the physical dimensions of the board and the source current
relative to the edge of the PCB, the SRF effects of the board can be dramatically
significant to the detriment of power plane performance, hence EMI emissions. By
undercutting the plane to the point of the last termination(s) that circumscribe the
devices that actually loads down the planes, the SRF performance of the board
can be dramatically improved, and yes, by factors as much as 2 or 3, but that
"assumes" that the initial board layout was sufficiently inappropriate to have
resulted in the SRF dropping to low as 200 to 400 MHz, due to physical
dimensions and stackup assignment.

For a properly designed PCB, the SRF is extremely high. Edge termination effects
and other design aspects, including use of discrete decoupling capacitors, lowers
the SRF of the finished assembly to about 200-400 MHz. This occurs if the board
is poorly designed. The 2 to 3 times multiple stated in my book brings up the SRF
back to where it should be. Clearly, if a board was "that" bad in SRF, then
appropriate terminations of the planes WOULD increase the performance by 2 or
3 times multiple, but that is not just 20-H per se. Other factors must be included in
the analysis. For boards that are poorly designed, the 20-H dimension would have
to be increased due to excessively large end stubs.

The overall concept is so simple how can one not visualize it?

The "20-H" rule, in this book, was not clearly stated to be the primary factor for the
increase in SRF, and I have endured harsh criticism because of that omission
based on the target audience for the book. The 20-H rule, by itself, is highly
effective in improving edge-effect terminations of circuit boards, and it is incorrect
to state that the 20-H rule, by itself, would cause the 2 to 3 times alteration, when
the precursor condition is that the planes be undercut to the point where they are
load-terminated WITHOUT edge stubs.

Printed Circuit Board Design Techniques for EMC Compliance - A Handbook for
Designers " has been 100% rewritten into a 2nd edition, and will be available late
May for purchase. This revised edition has a very detailed section that restates the
information above, adding this important component of discussion that was
omitted in the first edition, information for degreed engineers reading a book
written for the non-degreed.

In the original experiments of the 20-H concept, which is in fact only a plane-edge
flux termination concept (to bring the planes topologically to the point of the load
currents for termination) the physical dimensions of a 1206 resistor was of a size
that would result in an approximate "20-H" dimension. The omission concerning
the stub-edge primary concept in my book was unfortunate for members of si-list,
yet totally appropriate for thousands of PCB designers world wide who make
extensive use of this popular reference book without the need for theory or
mathematical analysis.

With this disclosure, I hope all questions and concerns have been answered and
the debate regarding whether 20-H is valid or not can forever cease. It is a
valuable design technique that is required with certain designs. Not all PCBs
require use of 20-H. This is where one must understand what is to be
accomplished, and how to implement this technique properly. In the past, fantastic
hints were provided by other professionals on si-list that alluded to my discussion
above. The hints that have been presented allows one the opportunity to think this
concept through and learn, which in turn makes us better engineers. Apparently,
there are still a large number of engineers that demand to be told everything, thus
never achieving personal technical excellence for themselves and their careers, by
blaming everyone and everything they can for things they do not understand,
including me, with unprofessional comments in a professional forum.

If additional knowledge is desired regarding 20-H, please refer to the 2nd edition
of my new book soon to be released.

--Mark Montrose--
Author of two IEEE Press books
Printed Circuit Board Design Techniques for EMC Compliance - A Handbook for
Designers and
EMC and the Printed Circuit Board - Design, Theory and Layout Made Simple.

[email protected] wrote:

> SI-LIST'ers,
> Page 54 of Mark I. Montrose's book "Printed Circuit Board Design Techniques for
> EMC Compliance" (IEEE Press, 1996) has the following statement:
> " Many multilayer PCBs generally have a self-resonant frequency between 200 and
> 400MHz. Use of the 20-H rule (see section 2.2) may increase the self-resonant
> frequency by a factor of 2 to 3."
> No where else have I found a mention of this effect. Following the 20-H rule
> on a board with 0.010" spacing between layers would amount to making the power
> plane 0.4" smaller in length and width than the ground plane. I don't see how
> such a small change in dimensions could cause such a huge reduction in
> inductance*capacitance that the second sentence suggests. Or could there be
> some kind of impedance matching because of the difference in the fringe fields
> at the edge of the power planes?
> Have any of you observed this effect, in measuring actual boards or in
> modelling? Thanks!
> John Barnes Advisory
> Engineer
> Lexmark International
> **** To unsubscribe from si-list or si-list-digest: send e-mail to [email protected] In the BODY of message put: UNSUBSCRIBE si-list or UNSUBSCRIBE si-list-digest, for more help, put HELP.
> si-list archives are accessible at
> ****

Scott McMorrow
Principal Engineer
SiQual, Signal Quality Engineering
18735 SW Boones Ferry Road
Tualatin, OR  97062-3090
(503) 885-1231

**** To unsubscribe from si-list or si-list-digest: send e-mail to [email protected] In the BODY of message put: UNSUBSCRIBE si-list or UNSUBSCRIBE si-list-digest, for more help, put HELP. si-list archives are accessible at ****

About this list Date view Thread view Subject view Author view

This archive was generated by hypermail 2b29 : Thu Apr 20 2000 - 11:36:10 PDT