RE: [SI-LIST] : Input switching threshold & CPCI

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From: Peterson, James F (FL51) (jfpeterson@space.honeywell.com)
Date: Tue Jan 04 2000 - 11:09:56 PST


Differential interfaces on a PCI-like bus....I think my I/O just got doubled
(from around 50 to 100). The old single-ended ttl-like PCI Bus still has
some punch : the 66MHZ/64bit version bursts at 528MB/s - let's see, that's
about 4Gbits/sec - certainly a nontrivial speed...

-----Original Message-----
From: D. C. Sessions [mailto:dc.sessions@vlsi.com]
Sent: Monday, January 03, 2000 11:40 AM
To: si-list@silab.eng.sun.com
Subject: Re: [SI-LIST] : Input switching threshold & CPCI

Jon Keeble wrote:
>
> I hear that the cpi/cpci guys are looking at a new termination technique
for
> backplanes that supports more devices on the bus with the existing
> controllers.
>
> I guess this involves parallel termination at both ends in Zo to Vt with
Vt
> close to the threshold region (?).
>
> How much variation in Vt exists across the range of controllers, and
across
> the range of fpgas and cplds that people use for pci?

PCI does the old (idiotic) 0.8-2.0 input thresholds that were first
documented on cave walls. In contrast, anyone trying to do serious
signaling at nontrivial speeds uses very tight thresholds, usually
scaled to the driver supply and usually with differential receivers.

The implications of this difference are left to the reader to infer.

-- 
D. C. Sessions
dc.sessions@vlsi.com

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