From: Robert Stuart (email@example.com)
Date: Sat Mar 25 2000 - 00:12:27 PST
I need to interface a Motorola DSP chip -- which operates at 3V3 and which
does not have 5V input tolerance -- to a legacy backplane that uses
nominally 5V TTL signals.
For some signals that are read from the backplane, I would like to specify a
simple (in logic terms) buffer that has this kind of performance:
* Output levels suitable for driving 3V3 parts if powered from 5V, or
* 5V input tolerance if powered from 3V3
* Low delay. preferably Pd lower than 4ns and 3ns would be better.
* drive suitable for 1 to 4 CMOS loads.
Since this will be a new logic family design-in I wondered if anyone had
useful suggestions/experience on which to use?
Fax 01480 451587
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