RE: [SI-LIST] : 10 layer board stackup

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From: cadpro2k@DACafe.com
Date: Fri Jan 21 2000 - 08:48:58 PST


Hi John,

Onething that hasn't been mentioned yet, or maybe I've overlooked it,
but what I've personally been involved with in the past is your IC power
filtering. You might have an EMI consultant look at how you're
filtering your IC pins. One board I designed the engineer wanted a
filter cap at EACH power pin (tied between the power pin and the
associated gnd pin), and an unusual amount of vias to the pwr/gnd planes
from these caps. I thought there was little basis to what he was asking,
but could I second guess him? Hah! Anyways, sure enough I also helped
out a colleague with a board design a few months later and when they had
the board tested, it failed emissions. The EMI consultant they used 1st!
suggested the addition of MANY filter caps, arranged around each IC, and
suggested a routing technique between the IC pin to caps to vias. He
also suggested guard traces around critial routes (nowdays we use extra
air gaps :), moving the critial (fast) routes to the inner layers,
adding layers, etc. etc.

Well, after a few weeks of redesign it was fab'd and tested. It passed
with excellent results.

But, how much is too much? I don't have that answer. I would suggest you
consult and EMI expert, have him (or them) look into the design, and get
recommendations. The one thing I personally agreed with the EMI
consultant on was the filtering additions (been there, seen that).

Good luck.

Mitch Morey
Sr PCB Designer
San Diego, CA

(snip)
> From: John Anderson [mailto:jpa@embedr.com]
> Sent: Thursday, January 20, 2000 3:55 PM
> To: Siganl Integrity Forum
> Subject: [SI-LIST] : 10 layer board stackup
>
> I presently have an 8 layer board as follows:
>
> sig top
> grd
> pwr
> internal 1
> internal 2
> pwr
> grd
> sig bottom
>(snip)
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