RE: [SI-LIST] : AC Coupling vs DC Coupling

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From: Degerstrom, Michael J. (degerstrom.michael@mayo.edu)
Date: Mon Apr 17 2000 - 19:13:23 PDT


I was thinking that Tony was getting off the subject somewhat. However,
what Tony is saying is that you do need to look at the whole picture.
I would try to simulate the difference between a poorly balanced code
versus a well balanced code. Then compare the difference to the
smearing of the eye due to SSN, pcb and connector crosstalk and so
on. If a non-coded bit pattern is still a major contributor to eye
pattern closure, then you will now know to spend more time to determine
whether to encode your data and/or improve your signal path. A word of
caution, however, when simulating long runs in a pcb. The loss can be
hard to predict with EM simulation. So the next board that I do where
loss may be important I am planning on first doing a quick test board to
tweek my lossy line model to match measurements.

By the way, we have used Tony's approach to run five parallel nets
with pcb crosstalk and package SSN (SSO) models to create eye diagrams.
These runs didn't take nearly 10 hours since we relied on HSPICE's
w-element model (which is apparently very computing efficient) for many
of coupling paths. The resulting eye patterns were very informative
and helped us to see things that we would normally have overlooked.

Mike

_______________________________________________________________
Mike Degerstrom Email: degerstrom.michael@mayo.edu
Mayo Clinic
200 1st Street SW
Gugg. Bldg. RM 1042A Phone: (507) 284-3292
Rochester, MN 55905 FAX: (507) 284-9171
WWW: http://www.mayo.edu/sppdg/sppdg_home_page.html
_______________________________________________________________

> -----Original Message-----
> From: Tony Sweeney [mailto:sween@lsil.com]
> Sent: Monday, April 17, 2000 5:38 PM
> To: si-list@silab.eng.sun.com
> Subject: Re: [SI-LIST] : AC Coupling vs DC Coupling
>
>
> I agree with Scott McMorrow's response and would like to add:
>
> Things like packages and connectors can be significant contributers to
> ISI. Another big contributer is SSO noise on the power supply
> lines and
> to
> a lesser extent crosstalk in the bondwires, package and board.
> Supply noise has the effect of modulating the buffer delay.
> So it would
> be helpful
> to model a group of 5 output buffers as follows.
>
> - model the chip to chip interconnect
> - buffer, bondwire, package, via, transmission line (lossy &
> coupled),
> via, package, bondwire, input buffer
> - you may have connectors and therefore multiple transmission
> lines also
> - model the power supply through the package
> - do not assume a perfect supply on the board
> - get bondwire, and package models that have coupling built in.
>
> - put a psuedo random bit pattern on the middle line
> - put a 1010 pattern on the other four lines
>
> - a big spice model like above and a 128 bit pattern would take ~10
> hours to run
> a single case (on a Sun server) so you might want to create a psuedo
> psuedo bit pattern.
>
> Simulation is a good tool but real boards are the only way to really
> know.
> HSPICE and XTK can be great tools to debug some obvious problems up
> front
> and you can see some things you cannot measure on the scope
> (true cycle
> by
> cyle setup and holds, true cyle to cyle jitter magnitudes).
>
> Regards,
>
> Tony
>
>
>
> Scott McMorrow wrote:
> >
> > "Greim, Michael" wrote:
> >
> > > What is an effective method of quantifying
> > > ISI's effect on jitter. Within a simulation, would
> > > the narrowing of an eye pattern indicate this.
> >
> > Yes, a good comparison would be to simulate
> > a pseudo random pattern and then compare it
> > to a simple pattern with a large number of ones
> > followed by a large number of zeros.
> >
> > >
> > > Would the difference between a pseudo random
> > > bit sequence and a clock creating the eye show
> > > this for a given topology?
> >
> > Yes, this third comparison is also quite useful
> >
> > regards,
> >
> > scott
> >
> > > Thanks for the help.
> > >
> > > MG
> > >
> > > > So ... whether on not non-DC balanced data will work in
> a system is
> > > > dependent upon the available jitter and skew margin at
> the receivers
> > > > and other sources of noise, jitter and skew in the
> system. ISI can
> > > > be simulated to determine the upper bounds on it's
> contribution to
> > > > jitter.
> > > >
> > >
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> >
> > --
> > Scott McMorrow
> > Principal Engineer
> > SiQual, Signal Quality Engineering
> > 18735 SW Boones Ferry Road
> > Tualatin, OR 97062-3090
> > (503) 885-1231
> > http://www.siqual.com
> >
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>
> --
> Anthony C. Sweeney
>
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