RE: [SI-LIST] : Bad IBIS models!

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From: Abe Riazi (ariazi@anigma.com)
Date: Sat Mar 18 2000 - 12:57:24 PST


Hi:

  After reading the messages in this thread, I noticed that many model
deficiencies have been pointed out by various authors. One additional
type of model defect worth mentioning, is that some models include false
logic threshold values. For example, an IBIS model may show Vinl = 0.8
V, Vinh = 2.0 v, when inapplicable. As explained in a previous post,
simulation of a receiver model possessing false thresholds may produce
results indicating invalid ringback violations or flight time values.

  Regards,
  Abe Riazi

-----Original Message-----
From: Scott McMorrow [mailto:scott@vasthorizons.com]
Sent: Wednesday, March 15, 2000 2:03 PM
To: si-list@silab.eng.sun.com
Subject: Re: [SI-LIST] : Bad IBIS models!

My major pet peeves:

Packages that are dead wrong.
... and most are.

Double counting die capacitance in with package
capacitance.

Ramps and Waveform tables created at high load resistance.

Min and Max waveform tables created at nominal voltage.

IV curves which don't pass through the origin.

Extracted parameters at typical corner only.

Loading that does not match the data sheet parameters.

... etc ... etc....

--
Scott McMorrow
Principal Engineer
SiQual, Signal Quality Engineering
18735 SW Boones Ferry Road
Tualatin, OR  97062-3090
(503) 885-1231
http://www.siqual.com

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