From: Abe Riazi ([email protected])
Date: Tue Jan 04 2000 - 22:57:25 PST
Dear All,
I like to comment on a critical relation between logic thresholds,
modeling and simulation. Some behavioral models contain the 0.8, 2.0 V
thresholds when inapplicable. A good example is the case of an IBIS
model designed for 3.3 V PCI simulation. I have attached below the
section of such example which includes the threshold voltages:
|
[Model] PCIIOBUF
Model_type I/O
Polarity Non-Inverting
Enable Active-Low
|Signals A, EN, PULLUP, PAD, VCCP, VSSP, VCC5REF
Vinl = 0.8V
Vinh = 2.0V
Vmeas = 1.50V
Cref = 50pF
Rref = 500
Vref = 0
|
|
|Variable typ min max
|
C_comp 4.00pF 1.80pF 6.00pF
[Temperature Range] 50.0 0 100
[Voltage range] 3.3V 3.0V 3.6V
|
Here, the model shows by mistake Vinl = 0.8V, Vinh = 2.0V, instead of
Vinl = 0.99V, Vinh = 1.65V (i.e. 0.3Vcc, 0.5Vcc). When above model is
simulated (as receiver), the results can flag ringback violations
following the rising or falling signal transitions, whereas the correct
thresholds may have not indicated such signal integrity degradation.
The receiver thresholds can also influence flight time values generated
via simulation. In short, receiver models with unreal switching
thresholds can cause real headache!
Abe
>----------
>From: D. C. Sessions[SMTP:[email protected]]
>Sent: Tuesday, January 04, 2000 9:44 AM
>To: [email protected]
>Subject: Re: [SI-LIST] : Input switching threshold & CPCI
>
>Abe Riazi wrote:
>>
>> D. C. Sessions Wrote:
>> >
>> >PCI does the old (idiotic) 0.8-2.0 input thresholds that were first
>> >documented on cave walls. In contrast, anyone trying to do serious
>> >signaling at nontrivial speeds uses very tight thresholds, usually
>> >scaled to the driver supply and usually with differential receivers.
>> >
>> Hi D. C.,
>>
>> This is a good point. For 3.3 V signaling, the input voltage threshold
>> values (based on PCI specs) consist of:
>>
>> Minimum Vih (Input High Voltage) = 0.5 Vcc
>> Maximum Vil (Input Low Voltage) = 0.3 Vcc
>
>Hmmm... 0.9v to 1.8v -- slightly tightened TTL again.
>The big evil of course is the 0.4 Vcc centerpoint, which
>Intel reflects in their drive specs making for rotten
>line matching. They made the same mistake with AGP
>(Vref of 0.39 to 0.41 Vcc, 2/3 PCI drive) even though
>there wasn't any need for backward compatibility.
>
>At least it's scaled. I'm tired of arguing with customers
>who insist on running timing analyses against Vih(max) at
>slow corner Vcc min.
>
>--
>D. C. Sessions
>[email protected]
>
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