Re: [SI-LIST] : LVDS driving PCML

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From: sweir (weirsp@a.crl.com)
Date: Wed Mar 08 2000 - 20:55:23 PST


Julia,

You need to stay in the CM range of the receiver. As the operating point
moves to the limits of the CM range the timing deteriorates. Somewhere
outside the published CM range the receiver does not function.

Regards,

Steve.

At 06:41 PM 3/8/00 -0800, you wrote:
>Dear SI-LIST,
>
>My question is about LVDS logic with Voh = 1.4V and Vol = 1.0V
>driving the PCML receiver. The problem is that the common mode voltage
>input range of the PCML receiver should not be less than 1.3 V (and not more
>than 2.0V).
>I really would like to terminate the differential transmission line with 100
>Ohm line-to-line resistor only.
>In that case I am out of the PCML common mode input range by 0.1 V.
>We HSPICEd this circuit and the simulator showed that even the common mode
>input voltage of 0.8 V would not be a problem.
>
>So, my question is, are there any hidden problems (reliability etc.) with
>this
>differential driver-receiver logic selection that
>I am not aware of?
>
>Thank you in advance,
>Julia Nekrylova
>
>
>Cyras Systems, Inc.
>
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