Re: [SI-LIST] : Clamp diodes in models (was Input switching threshold & CPCI)

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From: Scott McMorrow (scott@vasthorizons.com)
Date: Mon Jan 10 2000 - 16:24:58 PST


At SiQual we have seen several mechanisims of system
failure due to ("improper") diode clamping.

1) A phenomena known as "diode kickback" which is
a transmission line effect in CMOS driver and receiver circuits
when the diode is driver heavily into saturation. Essentially
the diode does not respond quick enough and stores
charge. This charge store keeps the diode forward biased
even after the normal reflection period is over. Current in the
circuit continues to flow until the diode turns off. When this
happens, a flyback effect occurs, causing a positive pulse
on the bus.

We have seen many devices that exhibit this failure mechanism,
especially on the PCI bus where excessive ground transients are
the norm. We have seen this occur with ASICs, Lan controller chips,
North and South Bridges, and even processors. The phenomena is
often misinterpreted and misdiagnosed as some other source of
noise. Often the device which fails, fails due to setup and hold
violations caused by this "kickback" launched by a totally different
device.

We have solved this problem with:

a) replacement of devices when possible ( unfortunately, due the
the large number of sole-source devices in most systems this is
usually not possible.)

b) exotic termination strategies with lots of simulation.

c) fast Schottky diode clamps at strategic points on the line.
(Note, however, that even Schottky clamps have only a limited
effect. They still present an impedance discontinuity on the bus
which must be dealt with. Often one cannot physically place the
clamp close enough to the device with the faulty clamp.)

2) SSI (Simultaneous Switching Input) noise. In this case, many
clamps with high negative transients can cause excessive current
on either the power or ground rails. 32 underdriven PCI bus signals
can cause over 1.25 amps of additional ground current to flow in
less than a nanosecond. We have seen this kind of excessive
current cause ground upset on receivers causing false clocking.
We have also seen it cause ground upset on drivers causing false
output transitions. We have even seen the effects on a totally
unrelated clock input on a device.

Generally the problem is due to inadequate ground and power pins
on the ground and vdd rings of the simultaneous switching inputs.
Input timings are not characterized into such excessive undershoot
conditions. The effect of this ground (or power) upset to other inputs
and outputs residing on the same ground or power ring is also not
usually characterized by the vendor. Although excessive drive
"droop" due to SSO can often be tolerated, the same SSI bounce
may not be characterized on the input receivers.

In both 1 and 2 above the serious problems which result are generally
catastrophic to reliable system operation. They are often known by
vendors and hidden by recommendations to not forward bias the
clamp diodes, or by "interesting" errata in released parts. One only
need look at simulation guidelines for certain processors from about
5 years ago, or eratta on production PCI south bridges, or DRAM
specifications to see that these problems are quite real.

regards,

scott

--
Scott McMorrow
Principal Engineer
SiQual, Signal Quality Engineering
18735 SW Boones Ferry Road
Tualatin, OR  97062-3090
(503) 885-1231
http://www.siqual.com

"Matt (boomer) Russell" wrote:

> Hi, > > just a comment, usually if this is a problem it is because it > violates long term reliability specs and will not really > be seen as an immediate failure. > > Usually it would be a violation of > 1) electromigration limits > 2) gate oxide overstress limits (maybe). > > Another issue is a fuzy one that is hard to > nail down and hard to quantify, and that is the > impact of noise injection into the chip supplies. > THis can be very design dependant and may only hit > at certain process corners and conditions. It could > cause timing violations or pll jitter, etc. > > matt > > Tom Dagostino wrote: > > > > We've measured 10's of thousands of I/O buffers to make models around here. > > Our internal spec is to push to part to at least 1 volt past the rail or at > > least 100 ma of current. In most cases we exceed these internal specs. It > > is rare that this causes any problems in the parts under test and in the > > cases where it has happened it seemed to be generic to a particular > > manufacturer's process. I cannot say what will happen over time from > > continous abuse like this. If you are seeing lots of failures then you are > > really putting more current into your devices than you may think. > > > > Tom Dagostino > > ICX Modeling Group > > tom_dagostino@mentor.com > > 503-685-1613 > > > > -----Original Message----- > > From: owner-si-list@silab.eng.sun.com > > [mailto:owner-si-list@silab.eng.sun.com]On Behalf Of Bradley S Henson > > Sent: Monday, January 10, 2000 8:02 AM > > To: si-list@silab.eng.sun.com > > Subject: Re: [SI-LIST] : Clamp diodes in models (was Input switching > > threshold & CPCI) > > > > Andrew, > > > > Please be carefull about "fixing" a model the vendor warns doesn't tolerate > > forward biasing of the "clamp diodes". While I agree that this sounds > > ridiculous, I have seen several parts from different vendors that suffered > > anomolous operation with very modest amount of over/undershoot. I found this > > on > > parts the vendors didn't warn about not tolerating overshoot. If a vendor > > explicitly warns you about this, you should investigate the robustness of > > their > > design, redesign to control the overshoot, or consider another part > > supplier. > > > > Good luck, > > > > Brad Henson, Raytheon > > > > "Ingraham, Andrew" <Andrew.Ingraham@compaq.com> on 01/08/2000 08:23:33 PM > > > > Please respond to si-list@silab.eng.sun.com > > > > To: "'si-list@silab.eng.sun.com'" > > <si-list@silab.eng.sun.com> > > > > cc: (bcc: Bradley S Henson/RWS/Raytheon/US) > > > > Subject: [SI-LIST] : Clamp diodes in models (was Input > > switching threshold & CPCI) > > > > Abe Riazi wrote: > > > > > This is interesting and I would like to share related thoughts and > > >experience. I have also received from some vendors behavioral models > > >which lacked POWER or GND clamp sections, in contradiction to the Bus > > >requirements or the actual device. > > > > > > Of course, this type of model defect is undesirable and requires > > >correction, as it can produce simulation results with invalid positive > > >or negative overshoot. > > > > I also have been given simulation models that lacked overshoot clamp > > characteristics. When queried, the IC vendor said that the signals at his > > chip's pins should *never* go even a bit below ground nor above Vdd, so it > > shouldn't matter to our simulations. Right! > > > > Many of us have also seen models with incredibly steep clamp diode curves. > > I don't know which is worse. > > > > **** To unsubscribe from si-list: send e-mail to > > majordomo@silab.eng.sun.com. In > > the BODY of message put: UNSUBSCRIBE si-list, for more help, put HELP. > > si-list archives are accessible at http://www.qsl.net/wb6tpu/si-list > > **** > > > > **** To unsubscribe from si-list: send e-mail to > > majordomo@silab.eng.sun.com. In the BODY of message put: UNSUBSCRIBE > > si-list, for more help, put HELP. > > si-list archives are accessible at http://www.qsl.net/wb6tpu/si-list > > **** > > > > **** To unsubscribe from si-list: send e-mail to majordomo@silab.eng.sun.com. In the BODY of message put: UNSUBSCRIBE si-list, for more help, put HELP. > > si-list archives are accessible at http://www.qsl.net/wb6tpu/si-list > > ****

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