From: Jeff (email@example.com)
Date: Tue Mar 14 2000 - 22:24:30 PST
--- Keith Amundsen <firstname.lastname@example.org> wrote:
> I have seen multiple lower-speed PLLs used in
> parallel to keep clock rates
> down but I have never heard of the approach you
Can you elaborate, or give some references on this?
Also, what do you mean by "keep clock rates down"?
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