RE: [SI-LIST] : tracking/oversampling PLL architectures

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From: Jeff (jeffd323@yahoo.com)
Date: Tue Mar 14 2000 - 22:24:30 PST


--- Keith Amundsen <kamundsen@cportcorp.com> wrote:
> Jim
> I have seen multiple lower-speed PLLs used in
> parallel to keep clock rates
> down but I have never heard of the approach you
> mentioned.

Can you elaborate, or give some references on this?
Also, what do you mean by "keep clock rates down"?

Jeff

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