[SI-LIST] : Hi Mr. Peters, I'm sorry that you foind our applications notes so confusing. If you can point out some of the specific areas of ambiguity we will attempt to correct them. With respect to your specific question below, i.e., where do you bring the feedback from, this is actually quite simple. You bring it from which ever pin you want to to achieve the multiply or divide ratio you want. The CY7B991 does not have a fixed output for feedback requirements. This can come from any output pin, and can even come from an external divider. The selection of a feedback output path to use is documented in a number of application notes available from http://www.cypress.com/clock/appnotes.html Regards, Ed Grivna Cypress Semiconductor Data Communications Division > From: "Andy Peters" <apeters@noao.edu> > To: <si-list@silab.eng.sun.com> > Subject: [SI-LIST] : PLL clock buffer chips and the feedback loop > Date: Mon, 3 Apr 2000 11:06:06 -0700 > MIME-Version: 1.0 > Content-Transfer-Encoding: 7bit > X-Priority: 3 (Normal) > X-MSMail-Priority: Normal > X-MimeOLE: Produced By Microsoft MimeOLE V4.72.2106.4 > Importance: Normal > > When using "zero-skew" PLL clock buffer chips (such as the Cypress > RoboClock), where do you bring the feedback from? Cypress' data sheets and > app notes are notoriously (and typically, I might add) unclear on this - > they simply indicate that it comes from "one of the outputs." > > For instance, my board has an FPGA that talks to four SDRAM devices. It > seems to me that one buffer output could drive the FPGA's clock pin (via > series termination) and four of the other outputs could drive the four SDRAM > clocks (again, through series terminations). Assume that my clock line > lengths are equal, to minimize board skew. Do I take the feedback from one > of the destination pins, and match the line length? Or is it sufficient to > simply connect one of the outputs to the feedback pin right at the chip? > > Are there any other vendors of these sorts of devices? Spread-spectrum > capability is not required. > > thanks, > > -andy > > ps: I sent a short e-mail to the sales-droids at Accel, asking some simple > questions about their signal integrity tool. Since they were apparently too > busy to bother replying, I am no longer considering their product. > > ----------------------------------------- > Andy Peters > Sr Electrical Engineer > National Optical Astronomy Observatories > 950 N Cherry Ave > Tucson, AZ 85719 > 520 318 8191 > apeters@noao.edu > > "Money is property; it is not speech." > -- Justice John Paul Stevens > > > **** To unsubscribe from si-list or si-list-digest: send e-mail to majordomo@silab.eng.sun.com. In the BODY of message put: UNSUBSCRIBE si-list or UNSUBSCRIBE si-list-digest, for more help, put HERe: [SI-LIST] : PLL clock buffer chips and the feedback loop

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From: Ed Grivna (elg@cypress.com)
Date: Tue Apr 11 2000 - 12:32:37 PDT


Hi Mr. Peters,

I'm sorry that you foind our applications notes so confusing.
If you can point out some of the specific areas of ambiguity
we will attempt to correct them.

With respect to your specific question below, i.e., where do you
bring the feedback from, this is actually quite simple. You
bring it from which ever pin you want to to achieve the multiply
or divide ratio you want. The CY7B991 does not have a fixed
output for feedback requirements. This can come from any output
pin, and can even come from an external divider.

The selection of a feedback output path to use is documented in
a number of application notes available from

http://www.cypress.com/clock/appnotes.html

Regards,

Ed Grivna
Cypress Semiconductor
Data Communications Division

> From: "Andy Peters" <
> Subject: [SI-LIST] : PLL clock buffer chips and the feedback loop
> Date: Mon, 3 Apr 2000 11:06:06 -0700
> MIME-Version: 1.0
> Content-Transfer-Encoding: 7bit
> X-Priority: 3 (Normal)
> X-MSMail-Priority: Normal
> X-MimeOLE: Produced By Microsoft MimeOLE V4.72.2106.4
> Importance: Normal
>
> When using "zero-skew" PLL clock buffer chips (such as the Cypress
> RoboClock), where do you bring the feedback from? Cypress' data sheets and
> app notes are notoriously (and typically, I might add) unclear on this -
> they simply indicate that it comes from "one of the outputs."
>
> For instance, my board has an FPGA that talks to four SDRAM devices. It
> seems to me that one buffer output could drive the FPGA's clock pin (via
> series termination) and four of the other outputs could drive the four SDRAM
> clocks (again, through series terminations). Assume that my clock line
> lengths are equal, to minimize board skew. Do I take the feedback from one
> of the destination pins, and match the line length? Or is it sufficient to
> simply connect one of the outputs to the feedback pin right at the chip?
>
> Are there any other vendors of these sorts of devices? Spread-spectrum
> capability is not required.
>
> thanks,
>
> -andy
>
> ps: I sent a short e-mail to the sales-droids at Accel, asking some simple
> questions about their signal integrity tool. Since they were apparently too
> busy to bother replying, I am no longer considering their product.
>
> -----------------------------------------
> Andy Peters
> Sr Electrical Engineer
> National Optical Astronomy Observatories
> 950 N Cherry Ave
> Tucson, AZ 85719
> 520 318 8191
>
http://www.qsl.net/wb6tpu
> ****

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