[SI-LIST] : SI Position available, Intel, Chandler - AZ

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From: Nerheim, Max (max.nerheim@intel.com)
Date: Wed Mar 29 2000 - 12:10:10 PST


Opening:

Intel has an immediate opening for an SI engineer in our validation group in
Chandler, Arizona. We build circuit boards to do validation of new chip
designs utilizing the latest microprocessor bus technology and high speed
design.

Duties include pre and post layout SI analysis of System Validation Circuit
Boards.

Intel offers a complete and competitive compensation package, including
profit sharing, 401K, stock purchase plan, and stock options. We have the
latest tools available in an atmosphere that fosters innovation and a take
charge work atmosphere. We value informed Risk Taking, High Quality, and
Results. We need someone that can work as a team member, assume
responsibility, and constructively confront and
solve problems.

The person will have an opportunity to influence the design of platforms
sold in millions of units per year.

Chandler is very warm in the summer, followed by 9 months of delightful
living.... Over 300 days of clear blue skies on average. Arizona has more
boats (and swimming pools?) per capita than any other state. Needless to
say, if you like water-skiing and water activities, one of the many Arizona
lakes are perfect to spend the summer weekends on........... A large
portion of the state is public land open for camping, hunting, 4-wheeling,
and outdoor activities. Unless you work for the US Post Office you would
know the Grand Canyon of the Colorado (river) is in Arizona - not Utah or
Colorado.......... Arizona has something for almost anyone.

The position involves simulation and analyzing of board level interfaces
between silicon products and external vendor products for high speed signal
parameters. The person must interface between chip design, marketing,
packaging technology, and board design teams to define the system
implementation boundaries that will meet internal specifications, customer
and manufacturing requirements. Deliverables include but are not limited to
customer design guidelines, IBIS models, and package ballout specifications.
Experience required in the following areas: basic circuit design (board,
chip and transistor level), high speed digital design, microprocessor level
system design, PCB layout, and PCB technology. Viewlogic XTK experience
highly desirable. Successful candidate will have at least three years
experience in the above areas with either a BSEE or MSEE degree.

Interested candidates may send an email with resume' to:

max.nerheim@intel.com

Thanks,
Max

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