RE: [SI-LIST] : Decoupling capacitor resonance

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From: Greim, Michael (mgreim@mc.com)
Date: Wed Jan 26 2000 - 06:11:32 PST


Hi Chris,

Well, I guess that the short answer is that as a rule of thumb
the following is not a bad way to go. However as you are aware
a capacitor can be modeled as a RLC combination. The impe-
dance of the decoupling bottoms out at the ESR of the resistor
when the C and L are in resonance. By using a number of caps
in parallel, you can lower the overall impedance of the system
(impedance halves for each doubling of quantity)

If you assume that the L is driven primarily by the package, the
C allows you to vary the resonant frequency of the circuit. Then
theres that ole I = C dV/dt thing to figure into the equation In
an ideal world you would like the resonance to be the frequency
that you need it. However, as long as your power system
impedance is lower than your design target, you should be
fine. Therefore, in theory, both caps could satisfy your need.

In closing, understand the rule that you are trying to solve and
select components appropriately. A simple rule of thumb will
not work for every one. Chip caps provide the effective decoupling
between the regions where tantalums and plane capacitance
are effective. Depending on your need, a single cap or group
of capacitor values may provide your solution.

Larry Smith et al, of Sun Microsystems has a good paper on
this topic that you might want to reference. It can be found
at:

http://www.qsl.net/wb6tpu/si_documents/docs.html

Best of Luck,

Michael Greim

> -----Original Message-----
> From: Chris Bobek [SMTP:cbobek@cadence.com]
> Sent: Tuesday, January 25, 2000 8:42 PM
> To: Si-list
> Subject: [SI-LIST] : Decoupling capacitor resonance
>
> Hi,
>
> There's been a lot of discussion about selecting the right decoupling
> capacitor(s) for an IC. Howard Johnson's philosophy seems to say "pick
> the largest value cap(s) in the smallest smt package that you can
> reliably purchase". I tend to agree with that. However, I have an
> appnote for a PLL (f~=50Mhz) that says to use a 22uF and a 10pF to
> properly decouple the device. Instead, I'm using a 22uF and a 0.1uF in
> the smallest package I'm allowed to procure (0805). FOR THE SAME SIZE
> PACKAGE, should I change the 0.1uF to 10pF? If so, why?
>
> My understanding is that the inductance of the 10pF and 0.1uF is almost
> equal (because they are in the same size package). Inductance being
> equal, the larger capacitance is better because it provides a lower
> impedance to ground. Therefore, using a 10pF would not gain us anything
> except an extra part to procure in addition to our ubiquitous 0.1uF's.
>
> Thank you for your help/insight,
>
> Chris
>
>
>
>
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