[SI-LIST] : High Speed Design by Rules of Thumb vs. Simulation

About this list Date view Thread view Subject view Author view

From: Abe Riazi (ariazi@anigma.com)
Date: Sat Feb 19 2000 - 08:37:19 PST

Dear Scholars:

 Before initiating a simulation, it is advisable for a SI engineer to
devote some thought to the question:

 Is simulation necessary for this design?

 The following paragraphs explore answers to above and related

  To my knowledge, high PCB speed designs performed without simulation
usually rely strongly on rules of thumb. That is, many critical
considerations such as the optimum trace lengths and separation,
stackup, routing topologies, decoupling, and termination are decided
upon by utilizing rules of thumb. These rules may be based on
designer's past experience or originate from technical publications. For
instance, there are documents by Micron, ATI, HP and Intel which provide
detailed guidelines for design of a high speed bus or even a complete
computer motherboard.

  Another approach aimed at eliminating or minimizing the need for
simulation is "scaling". It allows known results at one frequency to be
extended to another frequency, provided scaling factor requirements are
met by certain parameters of the topology traces, drivers and receivers.

  The prime motivation towards designing by rules of thumb is of course
to save money, by minimizing the need for SI analysis. However, high
speed PCB designs without simulation can increase possibility of
failures due to signal quality problems, or being too conservative (i.e
excessive termination, stackup, decoupling , etc., than optimally
needed) thereby greater manufacturing cost. Furthermore, a designer may
be often forced to make compromises or violate a rule of thumb. For
instance, the rule that a series terminator should be positioned very
close to the driver is frequently difficult to fulfill due to the PCB
space constraints. In general, as edge rates are decreasing and
solution space narrowing, it is becoming more difficult and risky to
design merely based on such guidelines.

 A powerful approach for appraisal of the need or lack thereof for
simulation is to compare trace and stub lengths to the critical length
Lc ( where, Lc = Tr/6D, with Tr representing signal rise time and D
propagation delay). When segments lengths in a topology are less than
Lc usually no simulation is required, and vice versa. Nevertheless,
there are noteworthy exceptions to this rule. As an example, the signal
behavior for certain cases ( such as a well matched network topology)
with long traces may be readily predictable without simulation by
applying the reflection coefficient formulas and associated transmission
line concepts. On the other hand, a net involving a strong low
impedance driver and a capacitive load may need to be simulated even for
trace lengths shorter than Lc.

   Speed and accuracy are among desired goals of a SI analysis.
Creating and maintaining a versatile library of high quality calibrated
models can aid efficiency. Formulating and writing a detailed plan
prior to start of a simulation task can also prove beneficial.

 In conclusion, high speed digital designs performed solely based on
rules of thumb (without simulation) are accompanied by increased risk of
failing due to SI deficiencies, or being too conservative hence more
costly. Simulation, although not always necessary, can significantly
enhance the chance of producing an optimally functioning device at the
first attempt. The critical line length offers a logical means for
evaluating the need for simulation. To maximize efficiency, it is
recommended to develop an extensive library of validated models, and to
contrive an effective plan before launching the simulation.

  Your comments are genuinely appreciated.


  Abe Riazi
  SI Engineer
  Anigma, Inc.

**** To unsubscribe from si-list or si-list-digest: send e-mail to majordomo@silab.eng.sun.com. In the BODY of message put: UNSUBSCRIBE si-list or UNSUBSCRIBE si-list-digest, for more help, put HELP.
si-list archives are accessible at http://www.qsl.net/wb6tpu

About this list Date view Thread view Subject view Author view

This archive was generated by hypermail 2b29 : Thu Apr 20 2000 - 11:35:06 PDT