RE: [SI-LIST] : LVDS driving PCML

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From: Degerstrom, Michael J. (degerstrom.michael@mayo.edu)
Date: Fri Mar 10 2000 - 17:44:11 PST


Julia,

Tom offers perhaps a good alternative. However, your data must be
DC balanced with 8b/10b coding, for example. Also, I'm not sure
if LVDS will be happy with no DC path between true and complement.
It seems viable, but I'd recommend simulating this approach.

I assume PCML is simply CML with positive supplies. Also I assume
that the CML parts you are evaluating are bipolar. If so,
it is possible to design an input with better CM range than
the classical current source pull-down input circuit. But, with
bipolar ckts, if you push the operating levels too much, you
start saturating the input transistors which is something you want
to avoid at all costs.

Mike
_______________________________________________________________
Mike Degerstrom Email: degerstrom.michael@mayo.edu
Mayo Clinic
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> -----Original Message-----
> From: Tom Dagostino [mailto:tom_dagostino@mentorg.com]
> Sent: Thursday, March 09, 2000 10:57 AM
> To: si-list@silab.eng.sun.com
> Subject: RE: [SI-LIST] : LVDS driving PCML
>
>
> If you are not going to operate with very low fequency data
> rates you might
> consider AC coupling the driver and receiver. Use dual
> resistors to the
> optimum CM voltage of the receiver to terminate the signal AC wise.
>
> Tom Dagostino
> ICX Modeling Group
> tom_dagostino@mentor.com
> 503-685-1613
>
>
> -----Original Message-----
> From: owner-si-list@silab.eng.sun.com
> [mailto:owner-si-list@silab.eng.sun.com]On Behalf Of sweir
> Sent: Wednesday, March 08, 2000 8:55 PM
> To: si-list@silab.eng.sun.com
> Subject: Re: [SI-LIST] : LVDS driving PCML
>
>
> Julia,
>
> You need to stay in the CM range of the receiver. As the
> operating point
> moves to the limits of the CM range the timing deteriorates.
> Somewhere
> outside the published CM range the receiver does not function.
>
> Regards,
>
>
>
> Steve.
>
> At 06:41 PM 3/8/00 -0800, you wrote:
> >Dear SI-LIST,
> >
> >My question is about LVDS logic with Voh = 1.4V and Vol = 1.0V
> >driving the PCML receiver. The problem is that the common
> mode voltage
> >input range of the PCML receiver should not be less than 1.3
> V (and not
> more
> >than 2.0V).
> >I really would like to terminate the differential
> transmission line with
> 100
> >Ohm line-to-line resistor only.
> >In that case I am out of the PCML common mode input range by 0.1 V.
> >We HSPICEd this circuit and the simulator showed that even
> the common mode
> >input voltage of 0.8 V would not be a problem.
> >
> >So, my question is, are there any hidden problems
> (reliability etc.) with
> >this
> >differential driver-receiver logic selection that
> >I am not aware of?
> >
> >Thank you in advance,
> >Julia Nekrylova
> >
> >
> >Cyras Systems, Inc.
> >
>

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