RE: [SI-LIST] : Clamp diodes in models (was Input switchingthresh old & CPCI)

About this list Date view Thread view Subject view Author view

From: Muranyi, Arpad (arpad.muranyi@intel.com)
Date: Mon Jan 10 2000 - 11:37:04 PST


To All interested,

The problem David states is actually not (primarily) caused by
capacitive effects. The problem is that the textbook diode
equations refer to the junction voltage, not the terminal voltage
of a device. In SPICE they do the same. The diode equations are
junction equations. If you plot the currents of such an equation
in any simple plotting tool (any spreadsheet, mathcad, etc.), you
will find that the current is very, very exponential, that is it
will go to kilo, Giga, etc. Amperes at very small forward bias
voltages, such as 1 volt.

However, since semiconductors are not superconductors, there is
always a resistive component in series with the junction which
is not part of these equations. The problem is that these
resistances default to zero in SPICE, so if a process model
maker does not explicitly put numbers in there for these
parameters, you will get the previously described perfect clamps.
If you had just one tenth of an Ohm as a series resistance in
the circuit, your maximum current would be less than 10 Amps
at 1 volts of forward bias (if not counting the 0.6 or so volts
of diode drop). Big difference!

It is not necessarily easy to get good numbers for these resistors.
Also, there are limitations in some SPICE tools for doing this correctly.
Remember, for a MOSFET there are Drain, Source and Substrate and their
resistances have to be modeled separately, otherwise the IV curve
of the channel (or the channel resistance) will also be effected.
The models showing such perfect clamping characteristics usually
have zero resistances in their process files.

The real problem is, however, that many process and/or chip designers
have no clue about transmission line effects, and rely on statements
which were mentioned in the previous postings: The signal should never
go outside the rail voltages. For this reason they feel justified to
ignore these effects. Wishful thinking... Sorry, but this
won't happen in the real world unless you terminate the heck out of
your system in a manner which includes the modal impedances too (even and
odd). This means that you will not only have to put termination resistors
between the traces and the reference plane, but also a resistor between each
trace in every possible combination... This is impossible from a parts
count and layout consideration point of view.

Arpad Muranyi
Intel Corporation
===================================================================

-----Original Message-----
From: David Haedge [mailto:d-haedge@raytheon.com]
Sent: Monday, January 10, 2000 9:10 AM
To: si-list@silab.eng.sun.com
Subject: [SI-LIST] : Clamp diodes in models (was Input
switchingthreshold & CPCI)

Fellow SIers,

I modeled a circuit using vendor provided SPICE models and noticed that the
undershoot in the SPICE *never* got below -.7 volts, but that my board
measurement was showing -2.5 to -3 volts for 1 or 2 nanoseconds, then
leveled
out at -.7 volts. I then asked the vendor why I was getting anomalous
results when the diode was forward biased. His answer was " Why would I
ever
want to forward bias the diode? They basically never expected the diodes to

be forward biased and therefore did not worry about model accuracy for that
condition. Further investigation revealed that it was next to impossible in
SPICE to accurately model both bias conditions in the same model. The
problem
as I understand it, is that when the diode becomes forward biased, it does
not does not absorb infinite current instantaneously, but the SPICE model
can
and does. There is a capacitance that needs to be charged before the diode
actually clamps. This is why I was seeing the -2.5 to -3.0 volt undershoot
for a couple of nanoseconds. Another SPICE device guy told me that you
really
need two separate and distinct diode models run in two different SPICE runs
to get the right answer. The same thing happens on overshoot. I am always
skeptical when I see nice straight lines at VSS-0.7 or VDD+.7 on any
simulation, SPICE, IBIS, or whatever.

David Haedge
Raytheon Company

**** To unsubscribe from si-list: send e-mail to
majordomo@silab.eng.sun.com. In the BODY of message put: UNSUBSCRIBE
si-list, for more help, put HELP.
si-list archives are accessible at http://www.qsl.net/wb6tpu/si-list
****

**** To unsubscribe from si-list: send e-mail to majordomo@silab.eng.sun.com. In the BODY of message put: UNSUBSCRIBE si-list, for more help, put HELP.
si-list archives are accessible at http://www.qsl.net/wb6tpu/si-list
****


About this list Date view Thread view Subject view Author view

This archive was generated by hypermail 2b29 : Thu Apr 20 2000 - 11:34:32 PDT