Re: [SI-LIST] : ESR and bypass caps

From: Larry Smith ([email protected])
Date: Fri Feb 04 2000 - 15:37:18 PST

Ron - Yes, there is a parallel resonance (high impedance) somewhere
between the series resonances every time you put two capacitors in
parallel. The trick is to make both of these resonances low Q and keep
the parallel resonances spaced closely in frequency. If we keep the
inductance down, we can use low ESR caps without getting into trouble.
The Q is about omega*L/ESR. As we go above 100 MHz, the skin effect
resistance (series) of the power planes also holds down the Q. In this
case, skin effect is working for us.

Then we have to space capacitors close together in value. This
prevents the parallel resonance from getting too high. The attached
spice deck and .pdf file shows two combinations of capacitors. The
first set has 5 closely spaced values and the second set has just two
values. Inductance is 1nH and ESR is 100mOhms:

xcap2 vdd 0 cap C=1.0n R=100m L=1n \$npo
xcap3 vdd 0 cap C=1.5n R=100m L=1n \$npo
xcap4 vdd 0 cap C=2.2n R=100m L=1n \$npo
xcap5 vdd 0 cap C=3.3n R=100m L=1n \$npo
xcap6 vdd 0 cap C=4.7n R=100m L=1n \$npo

...and...

xcap2 vdd 0 cap C=1.0n R=100m L=1n \$npo
xcap3 vdd 0 cap C=1.0n R=100m L=1n \$npo
xcap4 vdd 0 cap C=1.0n R=100m L=1n \$npo
xcap5 vdd 0 cap C=4.7n R=100m L=1n \$npo
xcap6 vdd 0 cap C=4.7n R=100m L=1n \$npo

From the spice output you can readily see the parallel resonance and
how dangerous it is when capacitors are not spaced closely in value.
(One ac amp has been forced into the parallel circuit, so volts is
interpreted as magnitude of impedance.) With the 5 different valued
capacitors, we see 4 parallel 'antiresonances', growing with increasing
frequency. The growth is because Q increases as omega increases. The
higher the resonant frequency, the more important it is to have low
inductance pads. The 5 capacitor-value case has a maximum impedance of
about 150 mOhm, but the 2 capacitor-value case has a maximum of about
600 mOhms. That is enough difference to make a product pass or fail.

With 5 capacitors, we have made a nice flat 100 mOhm impedance
between 60MHz and 200Mhz. With 50 capacitors, we could have made a
10 mOhm impedance between those frequencies. If only we could get a
bunch of 100 mOhm capacitors...

Members of the SI community should feel free to take this generic
spice deck and run it. Play around with ESR and inductance. You
will quickly see the value of using low ESR capacitors on low
inductance pads in managing a low impedance power system across
a broad frequency range. I believe the same results will be obtained
with Doug Brooks' simulator. Doug, please let us know.

regards,
Larry Smith
Sun Microsystems

> Date: Fri, 04 Feb 2000 11:43:31 -0800
> From: Ron Miller <[email protected]
>
> I agree with you totally but would like to add that there is a parallel
resonance near the series resonance for most chip capacitors not unlike a
crystals
> impedance. The lossiness of he PCB may smooth this out. ATC impedance
curves bear this out.
>
> Ron Miller

For SI list.

i1 vdd 0 ac=1 \$ frequency domain voltage source

xcap2 vdd 0 cap C=1.0n R=100m L=1n \$npo
xcap3 vdd 0 cap C=1.5n R=100m L=1n \$npo
xcap4 vdd 0 cap C=2.2n R=100m L=1n \$npo
xcap5 vdd 0 cap C=3.3n R=100m L=1n \$npo
xcap6 vdd 0 cap C=4.7n R=100m L=1n \$npo

rdum vdd 0 1e6 \$ keep spice happy

************** subcircuits *********************
.subckt cap 1 2 C=1 R=1 L=1
c 1 a c
r a b r
l b 2 l
.ends cap

***************************spice control*****************************
.options list node post=1 ingold=2
.ac dec 100 10X 1G

.alter
xcap2 vdd 0 cap C=1.0n R=100m L=1n \$npo
xcap3 vdd 0 cap C=1.0n R=100m L=1n \$npo
xcap4 vdd 0 cap C=1.0n R=100m L=1n \$npo
xcap5 vdd 0 cap C=4.7n R=100m L=1n \$npo
xcap6 vdd 0 cap C=4.7n R=100m L=1n \$npo

.end

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