Re: [SI-LIST] : High Speed Design by Rules of Thumb vs. Simulation

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From: Scott McMorrow ([email protected])
Date: Sun Feb 20 2000 - 23:48:29 PST


Here are my answers to the questions
you pose.

Abe Riazi wrote:

> A main objective of my post was to discuss possible solutions to
> following types of questions:
> Under what conditions is it necessary to simulate during the course of a
> high speed PCB design?

All conditions. Our experience has shown that the least likely signal is the
one which fails due to signalling issues. We simulate all nets on all designs
that are presented to us here at SiQual. To not do so would be
negligence on our part.

Our advise to our customers is to simulate early in the architecture phase
of a project, direct the architecture, part and driver selection process with
signal integrity simulations before they are fixed in concrete. Continue
to simulate in the placement phase to insure correct placement, and then
simulate continuously during the routing and cleanup phases to guarantee
design correctness.

When complete modeling is not available for all devices in a design
then a conservative best guess is indicated. We always opt for faster and
stronger than what we believe will occur in reality. We always note the
modeling trade offs that we make and try to err on the side of what we
believe to be worst case.

Simulation is easy compared to the alternative. At one job where I was
employed it was a matter of course to see 3, 4 or 5 board turns before
production. We did a cost analysis and determined that the cost of a
board turn during the pre-production beta phase of a program was
about $250,000 when we looked at all engineering, manufacturing,
testing and qualification costs. Since then, I vowed to reduce all designs
to 2 turns maximum, with a goal of no signal integrity or timing problems
on the first turn. The second turn was used to fix logic problems, feature
set problems and manufacturing yield issues.

We have been 100% successful in this regard since that time 6 years ago.

> What are the pros and cons of a high speed digital design based solely
> on rules of thumb?

The pros are that no thinking is necessary.

The cons are that if one does not think about the rules of thumb one might
forget the limits over which they are useful. Rules of thumb are useful as
long as the approximations which they are based on continue to hold
true. Unfortunately, those approximations and assumptions are rarely
well communicated initially and are often forgotten in the history of time.

Additionally, routed boards often do not quite follow the rules of thumb.
And those rules of thumb usually require manual human intervention
to implement and validate. If a human has to become involved in implementing
a rule of thumb and another is responsible for checking the rule
of thumb, then there is often a great chance of error during the design process.
I'd much rather take my chances with automated processes and
simulations to check for signalling issues in the design.

> By what means can efficiency of a SI simulation be optimized?

I'm not so sure what you mean here. If you mean analysis performance in terms
of accuracy and time to completion, then this is almost a non-issue these days.
Rarely do our simulations of complete boards for overshoot, undershoot, ringback,
crosstalk and timing issues take more than one day for small board and 3 days
for large boards. Occasionally we run across something that might take a week
of simulation time if run on one CPU. In these cases we split the load between
multiple processors.

If you mean the setup part of the process, then this is well sped up by the current
generation of tools which allow for GUI based rule entry and net classification,
along with scripting capability for more complex operations.

If you mean the modeling part of the process, then I would say that there is a need
to specialize in model creation and verification, to develop the expertise to know
how and when a model is technically correct, and when to make an informed
judgement in the face of little or no information. Continued pressure needs to be
appled to all device manufacturers to release reliable and accurate ibis and spice
models in a timely fashion..

> Now the complete answer to above can be quite lengthy encompassing many
> considerations and concepts, but as it was pointed out some key elements
> of the solution include:
> "Critical length"
> "Scaling"
> Economical considerations
> Development of a versatile model library
> Formulation of a comprehensive "simulation plan"

Critical length is not an issue. The only issue is desired accuracy, as is the case
in all engineering endeavours. Length is an artifact of what is truly desired,
a particular accuracy in terms of simulated voltages and times. Determine
what is reasonable accuracy for a typical design and the tools, methods and
simulation variables fall into place.

Scaling ... hmmm ... I'm not sure how this applies. What would one scale?
Simulators certainly scale fairly well in terms of performance.

Economical considerations are generally misunderstood. When a total cost analysis
is done it is amazing how quickly a Signal Integrity Engineering staff and tools will be
justified. Can you imagine trying to justify designing an ASIC and placing it into
production without timing verification and fault simulations?

> Additionally, the capabilities of the simulator program also plays an
> important role in this puzzle.

Indeed. If a particular simulator is not capable of the job it is being used for
then it should be replaced. Accuracy is no longer an issue except for 3-Dimensional
problems. Ease of use, ease of design setup and extensibility of features are the
key things that I look for in any tool. We tend to shun those that do not make our
job easier. We also look for the hidden unstated assumptions which lay at the
base of all simulators. I am often amazed at what I find ... both gems and coal.

Currently, we can bring a design into oursimulator and if we have all the models we can
have reliable simulations running with an hour. We can generally have a full board
crosstalk check done in 1 to 2 days. With the same simulator we can characterize
a complete design with multiple boards across the worst case design corners
in less than a week ... including the report generation. We use a fairly capable
simulation enviroment. And when that environment fails for a particular task
then we use a different environment.

What more could one ask for than good, efficient tools, the ability to use them
effectively and the capability of knowing when one is not so effective and must
be augmented with another which is more highly specialized.

best regards,


Scott McMorrow
Principal Engineer
SiQual, Signal Quality Engineering
18735 SW Boones Ferry Road
Tualatin, OR  97062-3090
(503) 885-1231

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