Re: [SI-LIST] : Input switching threshold & CPCI

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From: D. C. Sessions (dc.sessions@vlsi.com)
Date: Wed Jan 05 2000 - 11:25:41 PST


"Ingraham, Andrew" wrote:
>
> >> However, are you certain this model is for a part with 3.3V signaling
> >> levels? It's possible that this part is designed for "5V" switching
> levels
> >> but is powered by 3.3V (has 5V-compatible 3.3V outputs and 5V-tolerant
> >> inputs). The "VCC5REF" node is suspicious ... what would this be for in
> a
> >> 3.3V PCI signaling environment?
> >
> >High-side clamping. 5-v tolerant 3.3v devices need to bias the N-well up
> >to 5 volts to keep the parasitic drain-well diodes of the P-channel devices
> >from forward-biasing. (The gate logic behind them is -- ahem! -- exotic.)
>
> Well, then this IS a "5V" PCI device (despite making use of 3.3V power), and
> the 0.8V, 2.0V input thresholds ARE the correct ones.

Not really. The usual application uses 3.3v pullup devices (because, after all,
it *is* pulling up to 3.3v levels) and pulldowns that have extra drive on coming
out of tristate with a high-to-low transition (in case the line was charged to
5v). Receivers have 3.3v thresholds because they comply with the looser 5v
spec and, after all, they are being driven by 3.3v devices (there are no actual
5v parts left on the market, just 5v tolerant.)

The actual drive-and-receive circuitry is all 3.3v-compliant to allow it to be
used in 66 MHz busses. On a 66 MHz bus the well bias is tied to 3.3v and aside
from some minor additional circuitry in the drivers you have an ordinary 3.3v
PCI I/O.

-- 
D. C. Sessions
dc.sessions@vlsi.com

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