Re: [SI-LIST] : 10 layer board stackup

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From: Doug McKean (dmckean@corp.auspex.com)
Date: Fri Jan 21 2000 - 13:36:42 PST


Gary,

I'll have to ask -

1. How are you so sure fixing the board
   will solve the problem?

2. Do you know exactly the egress from which
   the emissions are coming?

It sounds as though there may not be options for
a recheck of the shielding. It could be a simple
grounding issue with a cable, a grounding issue
with the enclosure. Respinning a board just to
bury oscillator lines *may not* be the solution.

I've done it both ways - properly shielded noisy
boards so they weren't a problem and also designed
some boards to be extremely quiet. You're in a
good position to respin. Be careful. - Doug

"kogler@earthlink.net" wrote:
>
> I presently have an 8 layer board as follows:
>
> sig top
> grd
> pwr
> internal 1
> internal 2
> pwr
> grd
> sig bottom
>
> We failed radiated emissions. All clock/fast signals were routed on
> surface of board - since system is battery operated, ie keep the power
> consumption down. Routing these signals on inner layers will draw more
> power? Since we failed radiated emissions miserably, the plan is to now
> bury the clock signals on the inner layers. Emissions exceeded - out to
> 7th harmonic of clocks (19.66MHz - from which the following clocks are
> generated, 117.96MHz, 58.9824Mhz, and 29.4912MHz) Three other clocks
> are
> at 32.514MHz, 12.000MHz, and 24.576MHz. We are adding damping
> resistors.
> We are also adding 2 more signal layers to the board for the clock/fast
> signals - impossible to route clock signals on either internal 1 or 2,
> also under a time crunch. I am looking for advise on the board stackup
> for this now 10 layer board.
>
> Stackup as planned
>
> Sig top
> grd
> pwr 3.3V
> new layer for clocks/fast edge rates/repetitive
> internal 1
> internal 2
> new layer for clocks/fast edge rates/repetitive
> pwr 5V
> grd
> sig bottom
>
> Also checking into smaller decoupling capacitors - higher self-resonant
> frequency - presently my board has all decoupling capacitors with 0.1uF
> values.
>
> I have seen 10 layer stackups with pwr and grd layers separated by as
> many
> as 6 layers. I want to keep the pwr and grd layers close in my
> application
> for good board decoupling.
>
> Please email me at rwkinney@ra.rockwell.com as I will be offsite from my
> office for the next couple of weeks.
>
> Regards,
>
> Gary Steinkogler

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