[SI-LIST] : Job Opening- Intel Oregon

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From: Gardiner, Scott (scott.gardiner@intel.com)
Date: Wed Jan 26 2000 - 17:37:34 PST


Intel's desktop motherboard Core Technology Interconnect Design team is
growing and has an immediate opening for a Sr. Signal Integrity/Simulation
Engineer as well as an opening for a junior level Simulation Engineer. These
positions are available in Hillsboro, OR.

Focus will center around the design and development of digital high-speed
interfaces used on desktop motherboards. This includes the investigation of
new/developing interfaces and buses as well as dealing with leading edge CPU
and chipset technologies. Responsibilities will include developing and
evaluating simulation models, creating and refining simulation and timing
methodologies, and designing board level solution spaces. The Engineer will
also develop and drive correlation studies and measurements strategies to
validate simulations. Interface will occur between both board/system
designers and chip designers. Knowledge and experience with current design
tools such as SPECCTRAQUEST, HSPICE, and QUAD is typically required.
Backgrounds typically include transmission line & electromagnetic field
analysis, PCB design, and PC architecture. The candidate must be able to
work as a member of a team as well as independently.

The Senior level Engineer is expected to have a strong technical background
and posses leadership abilities necessary for leading a small team in the
area of high-speed digital interconnect design. A BS/MS in Electrical
Engineering (or equivalent) and 3 to 5+ years of relevant experience is
typically required.

Junior level engineer should have a minimum of a BSEE (or equivalent) with
1-2 yrs experience preferred. Coursework should include transmission line
analysis and understanding of Analog/Digital design concepts.

Again, positions are in Hillsboro (Portland), Oregon. If you are interested
in either of these positions, please send your resume to:

christopher.j.kelly@intel.com OR scott.gardiner@intel.com

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