From: S. Weir (firstname.lastname@example.org)
Date: Sat Mar 04 2000 - 04:05:53 PST
In general, I have to agree with Lee on this. While there are some very
specific exceptions, moating s/b avoided, especially if you don't fully
understand it. The most common side-effect of moating is that it forces
some monstrous effective loop area into a high-frequency current, ( read
radio antenna ), causing both the EMI problems that Lee is talking about,
as well as crosstalk problems. Ironically, sometimes the crosstalk appears
just where you may have thought you were preventing it.
For many problems, proper attention to component placement, stack-up,
signal routing, and adequate decoupling will solve any problems you might
have considered moating for. There are exceptions, but these tend to
involve situations where very high S/N ratios are required, such as
low-level analog, and RF receivers. If you search this thread you will
find a repeated theme that for the most part, continuous planes are your
At 04:46 PM 3/3/2000 -0800, you wrote:
>The problem with this technique is that modern ICs need decoupling
>capacitance at frequencies much higher than the bulk capacitors or any
>discrete capacitors can provide. That capacitance comes from the
>power plane structure. If you cut up you planes as you suggest, this will
>not be the case. Plane cuttnig is a bad idea. It produces more noise
>than it ever eliminates. Many EMI problems I fix are f
>rom the cutting of planes.
>In addition, wouldn't it be good to establish that there is some real
>noise problem before setting off to break up planes, add parts and
>increase product cost?
>Keith Amundsen wrote:
> > We have been looking at creative power plane connections. For
> subsystems on
> > a board (of one or more chips) we are considering isolating the power plane
> > under each of them. This would be done with a narrow moat between the
> > rectangular island and the rest of the power plane. The moat would be
> > bridged with ferrites. The island would have a bulk storage (10 or 33uF)
> > for each ferrite and a number of bypass (multiple values) capacitors for
> > each chip. These would be connected to the solid ground plane. Their are
> > many pros and cons to doing this and we thought a wider audience might
> > Comments?
> > -----Original Message-----
> > Subject: RE: [SI-LIST] : Adding inductors to ground?
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