RE: [SI-LIST] : 10 layer board stackup

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From: Cusanelli, Tony (Tony_Cusanelli@mentorg.com)
Date: Fri Jan 21 2000 - 05:33:11 PST


Gary,

  In addition to the suggestions you received from Tony and Lee, I suggest
that if you decide to go to 10 layers, the stackup you proposed will result
in inconsistent impedances (and reflected noise). You were considering four
signal layers next to each other. This will make the middle layers lose
their close proximity to the reference plane. I understand your desire to
maintain decoupling between the planes, however accomplishing that once
should be enough, you could afford to split one of the pairs.

  Also, Lee mentioned a review of the ground planes, I suggest looking at
the topology and termination of the clock lines. I had experience with
clocks on the outer layer of a board that simply needed to be configured in
a star pattern to eliminate an EMC problem.

  I also noticed that you questioned whether or not routing on the internal
layer would draw more power. This again would depend upon the impedance
values. If the internal layers are lower impedance, then yes it takes more
to drive them, but this is only a transient effect. The steady state (and
battery drain) will mostly be affected by the loads.

Regards

Tony Cusanelli - ICX Technical Specialist
http://www.mentor.com/icx
Phone 732-988-7920
Fax 732-988-7930
Voice Mail 908-604-0903

From: Dunbar, Tony [mailto:Tony_Dunbar@mentorg.com]

Gary,

Before you go throwing two more layers and a lot more dollars at this with,
as Lee points out, a high probability of still failing at a higher per-board
price, please tell us what post-route SI and/or EMC analysis or simulation
you have done. That may be a very worthwhile next step ahead of adding more
layers. Not only on this board but on all those that are to follow.

Often, signal integrity analysis can identify and head-off problems which
ultimately manifest themselves as EMC/EMI issues.

Tony Dunbar
tony_dunbar@mentorg.com

From: Lee Ritchey [mailto:leeritchey@earthlink.net]

My experience with problems like this has been that the emissions are
getting off the PCB on some unshielded wire or wires. As long as the power
planes
are continuous from side to side (you didn't mention how solid the power
planes are) clock traces on outer layers don't emit enough energy to fail,
even
CISPRB. So, if you just add more layers and "bury" the clocks, you are
likely to still fail, and in the bargain, the PCB will cost more.

Can you supply information on whether or not any of the power planes (ground
or Vcc) are split or have sections removed and what kinds of wires are
leaving
the PCB? That will be useful information on how to diagnose the problem.
Just adding layers, may not do it.

Lee

kogler@earthlink.net wrote:

> I presently have an 8 layer board as follows:
>
> sig top
> grd
> pwr
> internal 1
> internal 2
> pwr
> grd
> sig bottom
>
> We failed radiated emissions. All clock/fast signals were routed on
> surface of board - since system is battery operated, ie keep the power
> consumption down. Routing these signals on inner layers will draw more
> power? Since we failed radiated emissions miserably, the plan is to now
> bury the clock signals on the inner layers. Emissions exceeded - out to
> 7th harmonic of clocks (19.66MHz - from which the following clocks are
> generated, 117.96MHz, 58.9824Mhz, and 29.4912MHz) Three other clocks
> are
> at 32.514MHz, 12.000MHz, and 24.576MHz. We are adding damping
> resistors.
> We are also adding 2 more signal layers to the board for the clock/fast
> signals - impossible to route clock signals on either internal 1 or 2,
> also under a time crunch. I am looking for advise on the board stackup
> for this now 10 layer board.
>
> Stackup as planned
>
> Sig top
> grd
> pwr 3.3V
> new layer for clocks/fast edge rates/repetitive
> internal 1
> internal 2
> new layer for clocks/fast edge rates/repetitive
> pwr 5V
> grd
> sig bottom
>
> Also checking into smaller decoupling capacitors - higher self-resonant
> frequency - presently my board has all decoupling capacitors with 0.1uF
> values.
>
> I have seen 10 layer stackups with pwr and grd layers separated by as
> many
> as 6 layers. I want to keep the pwr and grd layers close in my
> application
> for good board decoupling.
>
> Please email me at rwkinney@ra.rockwell.com as I will be offsite from my
> office for the next couple of weeks.
>
> Regards,
>
> Gary Steinkogler
>
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