Re: [SI-LIST] : interplanar capacitance

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From: Ray Anderson (
Date: Thu Feb 03 2000 - 12:27:36 PST


        Rather than getting into the specifics of the particular
design you've submitted, I've got a few generalized comments on
stackups in general from an electrical perspective. There are a
lot of others on the list who can address the specifics of the
fabrication issues better than I can.

        Depending on the requirments of your project, the stackup
you've shown may or may not be adequate. In general, we tend to
try to put power/ground plane pairs next to each other with no
intervening signal lines between them. This is our best-case
scenario, of course it isn't always practical to do so.

        To maximize interplanar capacitance (which isn't really
such a big deal) and to minimize planar inductance (which is a
big deal), one should go for the smallest spacing between planes
practical. 4 mils is almost adequate for high performance designs,
2 mils is pretty good, and bleeding edge technologies allow you
to achieve sub-mil spacings.

        Minimizing the spacing increases the mutual coupling between
planes, minimizes the loop inductance seen by decoupling capacitors
which increases their efficiency and reduces the required number of
decaps. Going for minimum spacing also will allow your design to function
to higher frequencies where discrete bypass caps become ineffective.

        Some people advocate the use of high dielectric substrate
material to achieve increased interplane capacitance. Yes, it does
do that, but it doesn't do a thing for the inductance issue. Closer
spacing helps on both fronts.

        Anyway, thats my opinion :)
-Ray Anderson
Sun Microsystems

> Dear List Members,
> I have an eight layer board with four routing and four plane layers. The
> stackup I have chosen is;
> Primary side (signal) - contains all components
> +5V (full plane)
> Internal (signal)
> GND (full plane)
> +3.3V (full plane)
> Internal (signal)
> GND (full plane)
> Secondary side (signal) - no components
> I want to take advantage of the interplanar capacitance between planes GND
> and +3.3V. What core thickness should I specify? At what dimension
> (thickness of core) would I lose this advantage? Also, on the secondary
> side under an FPGA I have a large copper fill area that carries +2.5V, can I
> use the adjacent GND plane and this area fill for more decoupling. If so
> what thickness of prepreg should I specify? I would like to maintain a
> 0.062" overall thickness of the PWB.
> Thank you all,
> Ewart Speer
> Scientific Atlanta

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