[SI-LIST] : LVDS driving PCML

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From: Julia Nekrylova (julian@cyras.com)
Date: Wed Mar 08 2000 - 18:41:26 PST


Dear SI-LIST,

My question is about LVDS logic with Voh = 1.4V and Vol = 1.0V
driving the PCML receiver. The problem is that the common mode voltage
input range of the PCML receiver should not be less than 1.3 V (and not more
than 2.0V).
I really would like to terminate the differential transmission line with 100
Ohm line-to-line resistor only.
In that case I am out of the PCML common mode input range by 0.1 V.
We HSPICEd this circuit and the simulator showed that even the common mode
input voltage of 0.8 V would not be a problem.

So, my question is, are there any hidden problems (reliability etc.) with
this
differential driver-receiver logic selection that
I am not aware of?

Thank you in advance,
Julia Nekrylova

Cyras Systems, Inc.

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