Re: [SI-LIST] : Stack up

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From: sweir (weirsp@a.crl.com)
Date: Wed Feb 23 2000 - 12:37:05 PST


Lee,

I agree that with adequate spacing they can be routed on adjacent
layers. I think placing them on the same layer requires due respect for
the fact that LVDS should reflect against GND, and the PECL stuff should
reflect against its VCC. If the geometry allows this on the same layer, by
islanding, or splitting the adjacent plane layer, great. I think that case
is more likely the exception.

If the noise budget allows one or the other to reflect against the former's
reference plane, that is fine as well. But again, that is certainly not my
first choice, and I believe calls for detailed post-layout simulation.

What is your opinion w/regard to:

Top vs. TOP
VCCx GND
GND VCCx
SIG SIG
... ...
SIG SIG
GND VCCy
VCCy GND
Bottom Bottom

My opinion is that generally, the former is more advantageous than the
latter. What do you think?

Regards,

Steve.
At 07:51 AM 2/23/00 -0800, you wrote:
>I'm trying to say that PECL and LVDS can be routed on the same layer and
>achieve adequate isolation. Forcing separate layers for each technology
>complicates the design and potentially raises the cost
>unnecessarily.
>
>Lee
>
>sweir wrote:
>
> > Lee,
> >
> > Agreed. But moving the PECL away from a layer adjacent to the LVDS
> > guarantees the separation. Are you suggesting a better stackup, or more
> > questions before making a recommendation?
> >
> > Regards,
> >
> > Steve.
> > At 07:46 AM 2/22/00 -0800, you wrote:
> > >The PECL clocks don't need their own layer. Just make sure that the
> > >spacing between them and LVDS is large enough that the coupling is
> within spec.
> > >
> > >sweir wrote:
> > >
> > > > Iulian,
> > > >
> > > > If you need Sig5 for LVDS, get the PECL clocks out of Sig6. Also,
> do you
> > > > have a substantial number or single-ended signals? If so, you need
> to take
> > > > proper care to avoid crosstalk between those and the LVDS signals
> as well.
> > > >
> > > > Will the PECL clocks fit on signal bottom? If so, then I suggest the
> > > > following as a symmetric stack-up that will reduce your crosstalk
> problems
> > > > between the PECL clocks and LVDS:
> > > >
> > > > Signal top
> > > > 1.8
> > > > Gnd
> > > > S1
> > > > S2
> > > > Gnd
> > > > S3
> > > > S4
> > > > Gnd
> > > > S5
> > > > S6
> > > > Gnd
> > > > 3v3
> > > > Signal Bottom -Pecl clocks
> > > >
> > > > Regards,
> > > >
> > > > Steve.
> > > > At 11:23 AM 2/21/00 -0800, you wrote:
> > > >
> > > > >Hi
> > > > >
> > > > >I'm listening to this list for some time now and I would like to
> ask your
> > > > >opinion on a stack-up I'm working on.
> > > > > It is a board with 4x64 pairs of LVDS signals, 77.76 MHz
> > > clock, high
> > > > >speed(777.6 Hb/s).
> > > > >
> > > > > I came up with a 14 layers that looks like that:
> > > > >
> > > > >Signal top fanout, some analog power
> > > > >1.8V
> > > > >Gnd
> > > > >Sig1 LVDS
> > > > >Sig2 LVDS
> > > > >Gnd
> > > > >Sig3 LVDS
> > > > >Sig4 LVDS
> > > > >Gnd
> > > > >Sig5 LVDS
> > > > >Sig6 PECL clocks
> > > > >3.3V
> > > > >Gnd
> > > > >Signal bottom fanout
> > > > >
> > > > > I'll be using 1.6 mil core for my high speed cap.
> > > > > I would gladly use less layers, but I'm being forced by
> the HS3
> > > > >connectors.
> > > > >
> > > > > I would really appreciate your opinion.
> > > > >
> > > > >
> > > > >
> > > > >Thanks,
> > > > >
> > > > >Iulian Ungureanu
> > > > >PCB Designer
> > > > >PMC-Sierra,Inc.
> > > > >Iulian_Ungureanu@pmc-sierra.com
> > > > >http://www.pmc-sierra.com
> > > > >Voice:(604)415-6053 Ext.2586
> > > > >Fax:(604)415-6206
> > > > >
> > > > >
> > > > >
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