[SI-LIST] : interplanar capacitance

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From: Speer, Ewart (Ewart.Speer@sciatl.com)
Date: Thu Feb 03 2000 - 11:48:46 PST


Dear List Members,

I have an eight layer board with four routing and four plane layers. The
stackup I have chosen is;
        
        Primary side (signal) - contains all components
        +5V (full plane)
        Internal (signal)
        GND (full plane)
        +3.3V (full plane)
        Internal (signal)
        GND (full plane)
        Secondary side (signal) - no components

I want to take advantage of the interplanar capacitance between planes GND
and +3.3V. What core thickness should I specify? At what dimension
(thickness of core) would I lose this advantage? Also, on the secondary
side under an FPGA I have a large copper fill area that carries +2.5V, can I
use the adjacent GND plane and this area fill for more decoupling. If so
what thickness of prepreg should I specify? I would like to maintain a
0.062" overall thickness of the PWB.

Thank you all,
Ewart Speer
Scientific Atlanta

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