From: Vinu Arumugham (email@example.com)
Date: Fri Mar 17 2000 - 17:53:21 PST
Larry Smith wrote:
> Boy, I would not count on high power distribution impedance to slow
> down my edge rates. The edge rate would then be dependent on how many
> signals decided to switch at once. Timing would be a nightmare, not to
> mention SSN problems.
As I had mentioned before, S-G-S-S-P-S is not for designs where timing is critical. If timing were critical, one would probably go for a higher layer count board.
A higher PDS impedance would *reduce* SSN problems because the device would see ~n*Zpds where n is the no. of switching outputs, further reducing the edge rate.
And since not every design has a GHz system clock, a higher PDS impedance may have applications.
The following corollary may apply to SI/EMI:
Things should be made as slow as possible, never slower....
> We work very hard to provide low impedance, rock solid power supplies
> to the power pins of every chip. Let the chip determine the edge
> rate. Generally, we are trying to make the edges as fast as possible
> as we push to the very highest bandwidth possible. I know this is not
> what the EMI guys want to hear, but we must design them both fast and
> quiet. There is no market for the slow stuff. Anyway, it gives us all
> jobs and something to talk about.
> Larry Smith
> Sun Microsystems
> Vinu Arumugham wrote:
> > Larry Smith wrote:
> > > To directly answer Mark's questions, with the same amount of noise
> > > stimulation, there will be much more noise between the 40 mil power
> > > planes than between the 4 mil planes, in fact 10X. The reason is
> > > because of the increased impedance.
> > >
> > Doesn't increased power distribution impedance equate to slower logic transition
> times? If so, the amount of noise stimulation is not the same. If the design's timing
> margin allows for slower edge
> > rates, would 40 mil planes not be better than 4 mil planes?
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