RE: [SI-LIST] : tracking/oversampling PLL architectures

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From: Keith Amundsen ([email protected])
Date: Mon Mar 13 2000 - 12:01:08 PST


A Digital Phase Locked Loop (DPLL) is the oversampling variety. They may
have a tracking mode and a hold mode. In the tracking mode a special or
preamble pattern with maximum transition density is covenant to quickly
determine the bit centers for sampling. Then in the hold mode during random
data, the DPLL is not allowed to adjust anywhere near as often. Polynomial
scrambling circuits, turned on at the data source after the preamble ends,
etc., can be used to help ensure transitions during hold mode.
Regards, Keith

-----Original Message-----
From: Ooi, Thien Ern [mailto:[email protected]]
Sent: Friday, March 10, 2000 8:29 PM
To: '[email protected]'
Subject: RE: [SI-LIST] : tracking/oversampling PLL architectures

Once the appropriate sample has been determined, how frequently does the
sample choice need to be updated? Is a special data pattern needed to
update the sample choice, or random data will do, as long as there is a
certain minimum transistion density?

-----Original Message-----
From: [email protected] [mailto:[email protected]]
Sent: Thursday, March 09, 2000 1:56 AM
To: [email protected]
Subject: Re: [SI-LIST] : tracking/oversampling PLL architectures

<snipped>

In the oversampling PLL, which technically isn't a pll, a local and
relativly stable clock is used to sample the incoming bitstream several
times during each bit period. Logic then determines on a bit by bit
basis which of the several samples is the one to be used. You don't
actually have to have a local clock that is many times the frequency of
the bit rate, just generate several phases of a clock at the bit rate.

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